Yuanfeng Sun

According to our database, Yuanfeng Sun authored at least 6 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.

Yuanfeng Sun, Jian Qiao, Xueyi Yu, Woogeun Rhee, Byeong-Ha Park, Zhihua Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis.

Jun Li, Ni Xu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators.

Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang

IEEE J. Solid State Circuits, 2009

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.

Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Hyung Ki Ahn, Byeong-Ha Park, Zhihua Wang

IEEE J. Solid State Circuits, 2009

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.

Li Zhang, Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Dawn Wang, Zhihua Wang, Hongyi Chen

IEEE J. Solid State Circuits, 2009

2008

A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.

Xueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee, Zhihua Wang

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008