Xueyi Yu

According to our database1, Xueyi Yu authored at least 10 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2020
A Fractional-<i>N</i> PLL With Space-Time Averaging for Quantization Noise Reduction.
IEEE J. Solid State Circuits, 2020

2013
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators.
IEEE J. Solid State Circuits, 2009

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.
IEEE J. Solid State Circuits, 2009

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.
IEEE J. Solid State Circuits, 2009

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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