Yuji Terao

According to our database, Yuji Terao authored at least 2 papers between 2013 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013