Yuuki Ogata

According to our database, Yuuki Ogata authored at least 10 papers between 2003 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Energy Management of Smart Home by Model Predictive Control Based on EV State Prediction.

Yuuki Ogata, Toru Namerikawa

Proceedings of the 12th Asian Control Conference, 2019

2018

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

2017

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers.

Yukihiro Nakagawa, Takeshi Shimizu, Yoichi Koyanagi, Osamu Shiraki, Shinji Kobayashi, Kazuki Hyoudou, Takashi Miyoshi, Yuuki Ogata, Yasushi Umezawa, Takeshi Horie, Akira Hattori

Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications, 2010

2004

Building Smart Appliance Integration Middleware on the OSGi Framework.

Hiroo Ishikawa, Yuuki Ogata, Kazuto Adachi, Tatsuo Nakajima

Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004), 2004

2003

Requirements for a Component Framework of Future Ubiquitous Computing.

Hiroo Ishikawa, Yuuki Ogata, Kazuto Adachi, Tatsuo Nakajima

Proceedings of the 1st IEEE Workshop on Software Technologies for Future Embedded Systems, 2003