Hirotaka Tamura

According to our database, Hirotaka Tamura authored at least 80 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Nebula: Network Enhanced Boltzmann Machine With Universal Local Search Architecture.

Yasuhiro Watanabe, Hirotaka Tamura, Yuki Furue, Fang Yin

IEEE Access, 2024

Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.

Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

Optimization via Rejection-Free Partial Neighbor Search.

Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami

Stat. Comput., December, 2023

Generating gradients in the energy landscape using rectified linear type cost functions for efficiently solving 0/1 matrix factorization in Simulated Annealing.

Makiko Konoshima, Hirotaka Tamura, Yoshiyuki Kabashima

CoRR, 2023

Characterization of Locality in Spin States and Forced Moves for Optimizations.

Yoshiki Sato, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo

CoRR, 2023

Efficient correlation-based discretization of continuous variables for annealing machines.

Yuki Furue, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo

CoRR, 2023

2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization.

Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA.

Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021

Jump Markov chains and rejection-free Metropolis algorithms.

Jeffrey S. Rosenthal, Aki Dote, Keivan Dabiri, Hirotaka Tamura, Sigeng Chen, Ali Sheikholeslami

Comput. Stat., 2021

2020

Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial.

Keivan Dabiri, Mehrdad Malekmohammadi, Ali Sheikholeslami, Hirotaka Tamura

IEEE Trans. Parallel Distributed Syst., 2020

Derivation of QUBO formulations for sparse estimation.

Tomohiro Yokota, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo

CoRR, 2020

A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.

Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020

A Hamiltonian Engine for Radiotherapy Optimization.

Mehrdad Malekmohammadi, Keivan Dabiri, Joshua Mathews, Daryl Nazareth, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications.

Satoshi Matsubara, Motomu Takatsu, Toshiyuki Miyazawa, Takayuki Shibasaki, Yasuhiro Watanabe, Kazuya Takemoto, Hirotaka Tamura

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.

Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 30Gb/s 2x Half-Baud-Rate CDR.

Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

Physics-inspired optimization for constraint-satisfaction problems using a digital annealer.

Maliheh Aramon, Gili Rosenberg, Toshiyuki Miyazawa, Hirotaka Tamura, Helmut G. Katzgraber

CoRR, 2018

2017

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2017

Fast algorithm using summed area tables with unified layer performing convolution and average pooling.

Akihiko Kasagi, Tsuguchika Tabaru, Hirotaka Tamura

Proceedings of the 27th IEEE International Workshop on Machine Learning for Signal Processing, 2017

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine.

Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami

Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

Jitter injection for on-chip jitter measurement in PI-based CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR.

Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 3x blind ADC-based CDR for a 20 dB loss channel.

Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2015

A Reference-Less Single-Loop Half-Rate Binary CDR.

Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2015

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs.

Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.

Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI.

Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".

Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

Optimizing effective interconnect capacitance for FPGA power reduction.

Safeen Huda, Jason Helge Anderson, Hirotaka Tamura

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.

Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Blind Baud-Rate ADC-Based CDR.

Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Charge recycling for power reduction in FPGA interconnect.

Safeen Huda, Jason Helge Anderson, Hirotaka Tamura

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Design metrics for blind ADC-based wireline receivers.

Ali Sheikholeslami, Hirotaka Tamura

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.

Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS.

Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

IEEE J. Solid State Circuits, 2011

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

IEICE Trans. Electron., 2011

A pattern-guided adaptive equalizer in 65nm CMOS.

Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS.

Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.

Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.

Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa

IEEE J. Solid State Circuits, 2010

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2010

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

IEICE Trans. Electron., 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.

Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.

Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2008

2007

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.

Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2007

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX.

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2007

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance.

Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

IEEE J. Solid State Circuits, 2007

18-GHz Clock Distribution Using a Coupled VCO Array.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEICE Trans. Electron., 2007

A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX.

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.

Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa

IEICE Trans. Electron., 2006

A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid.

Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 3.2Gb/s Semi-Blind-Oversampling CDR.

Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers.

Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS.

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2005

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2005

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization.

Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura

IEEE J. Solid State Circuits, 2005

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.

Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

A CMOS multichannel 10-Gb/s transceiver.

Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

IEEE J. Solid State Circuits, 2003

1998

500-Mb/s nonprecharged data bus for high-speed DRAM's.

Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura

IEEE J. Solid State Circuits, 1998