Yasumoto Tomita

According to our database1, Yasumoto Tomita authored at least 19 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Acceleration of Structural Analysis Simulations using CNN-based Auto-Tuning of Solver Tolerance.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2018
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors.
IEEE J. Solid State Circuits, 2018

GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning.
Int. J. Netw. Comput., 2018

Speed-Up of Object Detection Neural Network with GPU.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017
An automated CNN recommendation system for image classification tasks.
Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

2016
An Automated CNN Recommendation System for Image Classification Tasks.
CoRR, 2016

An FPGA-accelerated partial duplicate image retrieval engine for a document search system.
Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016

An FPGA-accelerated partial image matching engine for massive media data searching systems.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Memory reduction method for deep neural network training.
Proceedings of the 26th IEEE International Workshop on Machine Learning for Signal Processing, 2016

2014
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.
Proceedings of the Symposium on VLSI Circuits, 2014

What is a good way to expand a silicon value to a solution value?
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2010
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron., 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.
IEEE J. Solid State Circuits, 2007

2006
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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