Yusuke Tokunaga

According to our database, Yusuke Tokunaga authored at least 10 papers between 1999 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

An Alternative Flocking Algorithm with Additional Dynamic Conditions.

Ningping Sun, Yusuke Tokunaga

Proceedings of the Ninth International Conference on Broadband and Wireless Computing, 2014

2012

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.

Koji Obata, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2010

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.

Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

IEEE J. Solid State Circuits, 2010

A 69.8 dB SNDR 3^rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.

Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.

Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.

Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.

Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho

IEEE J. Solid State Circuits, 2008

2006

A 0.03mm² 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface.

Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.

Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1999

Algorithm and Design of an Intelligent Digital Integrated Circuit for a Watermelon Harvesting Robot.

Yusuke Tokunaga, Toshihide Hakukawa, Takahiro Inoue

J. Robotics Mechatronics, 1999