Takuji Miki

Orcid: 0000-0002-0168-3304

According to our database1, Takuji Miki authored at least 29 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2024

Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection.
Proceedings of the 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2024

On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

2023
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging.
IEICE Trans. Electron., October, 2023

An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique.
IEICE Trans. Electron., October, 2023

A Triturated Sensing System.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Characterization of Backside ESD Impacts on Integrated Circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Physical Attack Protection Techniques for IC Chip Level Hardware Security.
IEEE Trans. Very Large Scale Integr. Syst., 2022

An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays.
IEICE Electron. Express, 2022

Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements.
IEEE Des. Test, 2022

Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2020
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.
IEEE J. Solid State Circuits, 2020

2019
A 0.72pJ/bit 400μm<sup>2</sup> Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes.
IEICE Trans. Electron., 2019

On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2017
A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC.
IEEE J. Solid State Circuits, 2017

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS.
IEICE Trans. Electron., 2017

2016
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits, 2015

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits, 2015

2014
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects.
IEEE J. Solid State Circuits, 2012

2009
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2006
Configurable multi-processor architecture and its processor element design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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