Koji Obata

According to our database1, Koji Obata authored at least 16 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits, 2015

Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex.
IEEE J. Solid State Circuits, 2015

2014
30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed P<sup>2</sup>ROM memory.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

30.2 Digital PWM-driven AMOLED display on flex reducing static power consumption.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method.
Proceedings of the Symposium on VLSI Circuits, 2012

2010
A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator.
IEEE J. Solid State Circuits, 2010

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.
IEICE Trans. Electron., 2010

A 69.8 dB SNDR 3<sup>rd</sup>-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Trans. Electron., 2007

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
A transduction-based framework to synthesize RSFQ circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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