Takashi Morie
Orcid: 0000-0003-2708-4307
According to our database1,
Takashi Morie
authored at least 118 papers
between 1994 and 2023.
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Bibliography
2023
A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design.
IEEE Trans. Neural Networks Learn. Syst., 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors.
Proceedings of the International Joint Conference on Neural Networks, 2023
2022
Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing.
IEEE Access, 2022
A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A memory-based entorhinal-hippocampal model and its FPGA implementation by on-chip RAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks.
CoRR, 2021
An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach.
IEEE Access, 2021
Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021
An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing.
Proceedings of the International Conference on Field-Programmable Technology, 2021
2020
Adv. Robotics, 2020
An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots.
IEEE Access, 2020
IEEE Access, 2020
2019
An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach.
CoRR, 2019
Live Demonstration: A VLSI Implementation of Time-Domain Analog Weighted-Sum Calculation Model for Intelligent Processing on Robots.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation.
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
2018
A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks.
CoRR, 2018
A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links.
J. Robotics Netw. Artif. Life, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the Neural Information Processing - 24th International Conference, 2017
2016
Proceedings of the 2016 Joint 8th International Conference on Soft Computing and Intelligent Systems (SCIS) and 17th International Symposium on Advanced Intelligent Systems (ISIS), 2016
A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2016, 2016
2015
IEEE J. Solid State Circuits, 2015
Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor.
J. Robotics Mechatronics, 2015
Neurocomputing, 2015
A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation.
Circuits Syst. Signal Process., 2015
A pixel-parallel state-propagation algorithm with self-update of propagation direction for subjective contour generation.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
2014
J. Robotics Netw. Artif. Life, 2014
A motion detection model inspired by hippocampal function and its applications to obstacle detection.
Neurocomputing, 2014
An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the Neural Information Processing - 21st International Conference, 2014
A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing.
Proceedings of the Neural Information Processing - 20th International Conference, 2013
2012
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects.
IEEE J. Solid State Circuits, 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012
Proceedings of the Computer Vision - ACCV 2012 Workshops, 2012
2011
Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation.
Proceedings of the Neural Information Processing - 18th International Conference, 2011
Proceedings of the Neural Information Processing - 18th International Conference, 2011
A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
An FPGA-Based Collision Warning System Using Moving-Object Detection Inspired by Neuronal Propagation in the Hippocampus.
Proceedings of the Brain-Inspired Information Technology, 2010
Real-Time Human-Machine Interaction System Based on Face Authentication and Arm Posture Recognition.
Proceedings of the Brain-Inspired Information Technology, 2010
Proceedings of the Brain-Inspired Information Technology, 2010
Artif. Life Robotics, 2010
Coarse Image Region Segmentation in Spatio-Temporal Domain Using a Region-based Coupled MRF Model with Phase Dynamics.
Aust. J. Intell. Inf. Process. Syst., 2010
Coarse Image Edge Detection using Self-adjusting Resistive-fuse Networks.
Proceedings of the Pattern Recognition in Information Systems, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Parametric Control in a Region-Based Coupled MRF Model with Phase Dynamics for Coarse Image Region Segmentation.
Proceedings of the 13th IEEE International Conference on Computational Science and Engineering, 2010
2009
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration.
IEEE J. Solid State Circuits, 2009
Single-Electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing.
Int. J. Nanotechnol. Mol. Comput., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the IEEE International Conference on Systems, 2009
A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Coarse image region segmentation using region-and boundary-based coupled MRF models and their PWM VLSI implementation.
Proceedings of the International Joint Conference on Neural Networks, 2009
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE International Conference on Systems, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter.
IEICE Trans. Electron., 2007
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach.
Proceedings of the Neural Information Processing, 14th International Conference, 2007
Proceedings of the 7th International Conference on Hybrid Intelligent Systems, 2007
CMOS circuit implementation of a coupled phase oscillator system using pulse modulation approach.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory.
IEICE Trans. Electron., 2006
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture.
IEICE Trans. Electron., 2006
A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit.
IEICE Trans. Electron., 2006
Intell. Autom. Soft Comput., 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
J. Robotics Mechatronics, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations.
Proceedings of the Advances in Natural Computation, First International Conference, 2005
2004
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture.
J. Intell. Fuzzy Syst., 2004
Intell. Autom. Soft Comput., 2004
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004
A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2003
2002
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process.
IEEE J. Solid State Circuits, 2002
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
IEEE J. Solid State Circuits, 2001
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution.
IEEE J. Solid State Circuits, 2001
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures.
Proceedings of the Advances in Neural Information Processing Systems 14 [Neural Information Processing Systems: Natural and Synthetic, 2001
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Pulse modulation circuit architecture and its application to functional image sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Quantitative characterization of substrate noise for physical design guides in digital circuits.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture.
Proceedings of the VLSI: Systems on a Chip, 1999
Measurements and analyses of substrate noise waveform in mixed signal IC environment.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998
Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998
1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
1994
IEEE J. Solid State Circuits, September, 1994