Shiro Dosho

According to our database1, Shiro Dosho authored at least 31 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers.
IEICE Electron. Express, 2018

2017
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique.
IEEE J. Solid State Circuits, 2017

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS.
IEICE Trans. Electron., 2017

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits, 2015

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits, 2015

2014
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells.
IEICE Trans. Electron., 2013

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs.
IEEE J. Solid State Circuits, 2012

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects.
IEEE J. Solid State Circuits, 2012

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey.
IEICE Trans. Electron., 2012

Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters.
IEICE Trans. Electron., 2012

Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration.
IEEE J. Solid State Circuits, 2011

2010
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.
IEEE J. Solid State Circuits, 2010

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator.
IEEE J. Solid State Circuits, 2010

A 69.8 dB SNDR 3<sup>rd</sup>-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration.
IEEE J. Solid State Circuits, 2009

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.
IEEE J. Solid State Circuits, 2008

2007
An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter.
IEICE Trans. Electron., 2007

2006
A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit.
IEICE Trans. Electron., 2006

A 0.03mm<sup>2</sup> 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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