Yuta Tokusashi

Orcid: 0000-0001-8757-1938

According to our database1, Yuta Tokusashi authored at least 15 papers between 2015 and 2023.

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Bibliography

2023
Demo: Enabling DNN Inference in the Network Data Plane.
Proceedings of the 6th on European P4 Workshop, 2023

2021
NRG: A Network Perspective on Applications' Performance.
Proceedings of the 5th Network Traffic Measurement and Analysis Conference, 2021

2019
An FPGA-Based Change-Point Detection for 10Gbps Packet Stream.
IEICE Trans. Inf. Syst., 2019

The Case For In-Network Computing On Demand.
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

Key-value Store Chip Design for Low Power Consumption.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018
LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store.
CoRR, 2018

LaKe: The Power of In-Network Computing.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Accelerating Blockchain Transfer System Using FPGA-Based NIC.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

Network Optimizations on Prediction Server with Multiple Predictors.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC.
Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018

2017
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches.
IEEE Micro, 2017

2016
A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016

NOSQL hardware appliance with multiple data structure.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface.
SIGARCH Comput. Archit. News, 2015


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