Zehan Cui

According to our database1, Zehan Cui authored at least 18 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

Cracking Intel Sandy Bridge's Cache Hash Function.
CoRR, 2015

Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface.
CoRR, 2015

BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems.
ACM Trans. Archit. Code Optim., 2014

HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap.
ACM Trans. Archit. Code Optim., 2014

MIMS: Towards a Message Interface Based Memory System.
J. Comput. Sci. Technol., 2014

CMD: classification-based memory deduplication through page access characteristics.
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014

Going vertical in memory management: Handling multiplicity by multi-policy.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

DTail: a flexible approach to DRAM refresh management.
Proceedings of the 2014 International Conference on Supercomputing, 2014

A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

MIMS: Towards a Message Interface based Memory System
CoRR, 2013

A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture.
Proceedings of the 12th IEEE International Conference on Trust, 2013

Scattered superpage: A case for bridging the gap between superpage and page coloring.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A lightweight hybrid hardware/software approach for object-relative memory profiling.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Evaluation and Optimization of Breadth-First Search on NUMA Cluster.
Proceedings of the 2012 IEEE International Conference on Cluster Computing, 2012

A software memory partition approach for eliminating bank-level interference in multicore systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

HaLock: hardware-assisted lock contention detection in multithreaded applications.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

A fine-grained component-level power measurement method.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011