Zijian Huang

Orcid: 0009-0002-8166-0969

Affiliations:

Fudan University, School of Microelectronics, Shanghai, China

According to our database¹, Zijian Huang authored at least 7 papers between 2025 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2026

DeepPiC: xPU-PIM Cluster Architecture with Adaptive Resource-Aware Task Orchestration for DeepSeek-Style MoE Inference.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

GPOS: A General and Precise Offloading Strategy for High Generality of DNN Acceleration by OCP and NDP Co-Optimizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2025

Digital Predistortion of Quadrature Digital Power Amplifiers Using RVRTCNN: Real-Valued Residual Temporal Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Commun. Lett., September, 2025

APCPU: Adaptive-Pooling Compression Processing Unit for Energy-Efficient DNNs Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

CPSnB: Compressing and Processing Spatial Similarity near Memory Bank for DNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Zijian Huang

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