Yinyin Lin
Orcid: 0000-0002-5939-3502
According to our database1,
Yinyin Lin
authored at least 29 papers
between 2006 and 2023.
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Bibliography
2023
ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation.
IEEE Access, 2023
2022
Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Computers, 2017
3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.
Microelectron. J., 2017
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEICE Electron. Express, 2016
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage.
IEICE Electron. Express, 2012
Variation-tolerant Cu<sub>x</sub>Si<sub>y</sub>O-based RRAM for low power application.
IEICE Electron. Express, 2012
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEICE Electron. Express, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
2007
2006
Characterization of Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> thin film transistor and its application in non-volatile memory.
Microelectron. J., 2006