Haidong Tian

According to our database, Haidong Tian authored at least 8 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

MPiCO: Memory-Pool-Based XPU-PIM Cluster over Optical I/O with Load-Imbalance-Aware Assignment and Execution-Site-Matching Mapping Strategies for MoE Inference.

Zixu Li, Yinyin Lin, Chengchen Wang, Yong Wang, Haidong Tian, Xiankui Xiong

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

DeepPiC: xPU-PIM Cluster Architecture with Adaptive Resource-Aware Task Orchestration for DeepSeek-Style MoE Inference.

Zixu Li, Manni Li, Zijian Huang, Jiayu Yang, Wending Zhao, Yinyin Lin, Chengchen Wang, Haidong Tian, Xiankui Xiong

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

LsCMM-H: A TCO-Optimized Hybrid CXL Memory Expansion Architecture with Log Structure.

Xingyu Chen, Xiangrui Zhang, Sirui Peng, Zhiwang Guo, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test.

Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.

Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.

Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2023

2021

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.

Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie

Proceedings of the 14th IEEE International Conference on ASIC, 2021