Xiankui Xiong

Orcid: 0009-0009-5194-6174

According to our database1, Xiankui Xiong authored at least 18 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Fast Transform Kernel Selection Based on Frequency Matching and Probability Model for AV1.
IEEE Trans. Broadcast., June, 2024

LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

SFFTNet: Sparse Feature Fusion Transformer Network for Image Deblurring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

FullSparse: A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023

Luminance-Preserving Visible and Near-Infrared Image Fusion Network with Edge Guidance.
Proceedings of the IEEE International Conference on Image Processing, 2023

TPNoC: An Efficient Topology Reconfigurable NoC Generator.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Graph Representation Learning for Microarchitecture Design Space Exploration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Performance Error Evaluation of gem5 Simulator for ARM Server.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Automated Compiler for RISC-V Based DNN Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Design of 16TOPS Efficient GEMM Module in Deep Learning Accelerator.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2017
On-line memorry defragmentation for NVM-based persistent heaps.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017


  Loading...