Ziyun Li

Orcid: 0000-0003-4286-9030

According to our database1, Ziyun Li authored at least 38 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
ImbaGCD: Imbalanced Generalized Category Discovery.
CoRR, 2024

Generalized Categories Discovery for Long-tailed Recognition.
CoRR, 2024

2023
EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Hardware Co-Design.
IEEE Micro, 2023

Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications.
IEEE Micro, 2023

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.
CoRR, 2023

Supervised Knowledge May Hurt Novel Class Discovery Performance.
CoRR, 2023

SMKD: Selective Mutual Knowledge Distillation.
Proceedings of the International Joint Conference on Neural Networks, 2023

Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Fully-Binarized Distance Computation based On-device Few-Shot Learning for XR applications.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
A Closer Look at Novel Class Discovery from the Labeled Set.
CoRR, 2022

Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications.
CoRR, 2022

Distributed On-Sensor Compute System for AR/VR Devices: A Semi-Analytical Simulation Framework for Power Estimation.
CoRR, 2022

i-FlatCam: A 253 FPS, 91.49 µJ/Frame Ultra-Compact Intelligent Lensless Camera for Real-Time and Efficient Eye Tracking in VR/AR.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

EyeCoD: eye tracking system acceleration via flatcam-based algorithm & accelerator co-design.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

SplitNets: Designing Neural Architectures for Efficient Distributed Computing on Head-Mounted Systems.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.
IEEE J. Solid State Circuits, 2021

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.
IEEE J. Solid State Circuits, 2021

Not All Knowledge Is Created Equal.
CoRR, 2021

2020
Style-adaptive photo aesthetic rating via convolutional neural networks and multi-task learning.
Neurocomputing, 2020

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

AA-ResNet: Energy Efficient All-Analog ResNet Accelerator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications.
IEEE Trans. Circuits Syst. Video Technol., 2019

A 1920 $\times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching.
IEEE J. Solid State Circuits, 2019

An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles.
IEEE J. Solid State Circuits, 2018

A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Convolutional neural networks for intestinal hemorrhage detection in wireless capsule endoscopy images.
Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

2016
A 10 mm<sup>3</sup> Inductive Coupling Radio for Syringe-Implantable Smart Sensor Nodes.
IEEE J. Solid State Circuits, 2016

Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Vision Applications.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

26.7 A 10mm3 syringe-implantable near-field radio system on glass substrate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Low complexity optical flow using neighbor-guided semi-global matching.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System.
IEEE J. Solid State Circuits, 2015

2014
Dissection simulation of deformable objects using the extended finite element method.
Proceedings of the 2014 IEEE International Symposium on Haptic, 2014


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