Chaitali Chakrabarti

Orcid: 0000-0002-9859-7778

According to our database1, Chaitali Chakrabarti authored at least 272 papers between 1990 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to low power embedded system design and to very large scale integration architectures for signal processing".

Timeline

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On csauthors.net:

Bibliography

2024
PED: Probabilistic Energy-efficient Deadline-aware scheduler for heterogeneous SoCs.
J. Syst. Archit., February, 2024

FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs).
IEEE Des. Test, February, 2024

Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs.
IEEE Trans. Computers, January, 2024

EMGAN: Early-Mix-GAN on Extracting Server-Side Model in Split Federated Learning.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Communications and High-Precision Positioning (CHP2): Hardware Architecture, Implementation, and Validation.
Sensors, February, 2023

Proactively Predicting Dynamic 6G Link Blockages Using LiDAR and In-Band Signatures.
IEEE Open J. Commun. Soc., 2023

Model Extraction Attacks on Split Federated Learning.
CoRR, 2023

Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.
CoRR, 2023

MocoSFL: enabling cross-client collaborative self-supervised learning.
Proceedings of the Eleventh International Conference on Learning Representations, 2023

Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
Energy and Loss-aware Selective Updating for SplitFed Learning with Energy Harvesting-Powered Devices.
J. Signal Process. Syst., 2022

Probabilistic Risk-Aware Scheduling with Deadline Constraint for Heterogeneous SoCs.
ACM Trans. Embed. Comput. Syst., 2022

T-BFA: Targeted Bit-Flip Adversarial Weight Attack.
IEEE Trans. Pattern Anal. Mach. Intell., 2022

Blockage Prediction Using Wireless Signatures: Deep Learning Enables Real-World Demonstration.
IEEE Open J. Commun. Soc., 2022

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2022

LiDAR-Aided Mobile Blockage Prediction in Real-World Millimeter Wave Systems.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2022

An Adjustable Farthest Point Sampling Method for Approximately-sorted Point Cloud Data.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022

Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Deep Learning for Moving Blockage Prediction using Real mmWave Measurements.
Proceedings of the IEEE International Conference on Communications, 2022

ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021

RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.
CoRR, 2021

Deep Learning for Moving Blockage Prediction using Real Millimeter Wave Measurements.
CoRR, 2021

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Computationally-efficient voice activity detection based on deep neural networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Communication and Computation Reduction for Split Learning using Asynchronous Training.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Parallel Gibbs Sampler for Wavelet-Based Bayesian Compressive Sensing with High Reconstruction Accuracy.
J. Signal Process. Syst., 2020

Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging.
IEEE Trans. Computers, 2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs.
IEEE Des. Test, 2020

Automated Parallel Kernel Extraction from Dynamic Application Traces.
CoRR, 2020

Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity.
Proceedings of the Interspeech 2020, 2020

Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Defending Bit-Flip Attack through DNN Weight Reconstruction.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Defending and Harnessing the Bit-Flip Based Adversarial Weight Attack.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications.
IEEE Trans. Circuits Syst. Video Technol., 2019

Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems.
IEEE Trans. Computers, 2019

MAX<sup>2</sup>: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Articulation constrained learning with application to speech emotion recognition.
EURASIP J. Audio Speech Music. Process., 2019

A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors.
IEEE Comput. Archit. Lett., 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Improving Reliability of ReRAM-Based DNN Implementation through Novel Weight Distribution.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Residual + Capsule Networks (ResCap) for Simultaneous Single-Channel Overlapped Keyword Recognition.
Proceedings of the Interspeech 2019, 2019

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Reducing Energy of Baseband Processor for IoT Terminals with Long Range Wireless Communications.
J. Signal Process. Syst., 2018

A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware.
J. Signal Process. Syst., 2018

Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance.
IEEE Trans. Multi Scale Comput. Syst., 2017

Fluid wireless protocols: energy-efficient design and implementation.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Low-power neuromorphic speech recognition engine with coarse-grain sparsity.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems.
IEEE Trans. Computers, 2016

RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory.
ACM Trans. Archit. Code Optim., 2016

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Low Complexity 3D Ultrasound Imaging Using Synthetic Aperture Sequential Beamforming.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Vision Applications.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Checkpointing Exascale Memory Systems with Existing Memory Technologies.
Proceedings of the Second International Symposium on Memory Systems, 2016

Design of a reliable RRAM-based PUF for compact hardware security primitives.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low complexity optical flow using neighbor-guided semi-global matching.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Low power baseband processor for IoT terminals with long range wireless communications.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

2015
Using Graphics Processing Units in an LTE Base Station.
J. Signal Process. Syst., 2015

High Frame Rate 3-D Ultrasound Imaging Using Separable Beamforming.
J. Signal Process. Syst., 2015

Separable Beamforming For 3-D Medical Ultrasound Imaging.
IEEE Trans. Signal Process., 2015

Within and cross-corpus speech emotion recognition using latent topic model-based features.
EURASIP J. Audio Speech Music. Process., 2015

An overview of recent advances on distributed and agile sensing algorithms and implementation.
Digit. Signal Process., 2015

Low cost clutter filter for 3D ultrasonic flow estimation.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A fixed-point neural network for keyword detection on resource constrained hardware.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram.
J. Signal Process. Syst., 2014

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding.
J. Signal Process. Syst., 2014

A Distributed Canny Edge Detector: Algorithm and FPGA Implementation.
IEEE Trans. Image Process., 2014

Sonic Millip3De: An Architecture for Handheld 3D Ultrasound.
IEEE Micro, 2014

A low complexity scheme for accurate 3D velocity estimation in ultrasound systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Image processing using approximate datapath units.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A multi-modal approach to emotion recognition using undirected topic models.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A hybrid approach to offloading mobile image classification.
Proceedings of the IEEE International Conference on Acoustics, 2014

2013
Multi-source Neural Activity Estimation and Sensor Scheduling: Algorithms and Hardware Implementation.
J. Signal Process. Syst., 2013

Hardware Acceleration for Neuromorphic Vision Algorithms.
J. Signal Process. Syst., 2013

Techniques for Compensating Memory Errors in JPEG2000.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Bayesian Tracking of Multiple Sources of Neural Activity: Algorithms and Real-Time FPGA Implementation.
IEEE Trans. Signal Process., 2013

Energy and Quality-Aware Multimedia Signal Processing.
IEEE Trans. Multim., 2013

Architecting an LTE base station with graphics processing units.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Separable beamforming for 3-D synthetic aperture ultrasound imaging.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

A parallel stochastic computing system with improved accuracy.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Exploring DRAM organizations for energy-efficient and resilient exascale memories.
Proceedings of the International Conference for High Performance Computing, 2013

Parallelization techniques for implementing trellis algorithms on graphics processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

WiBench: An open source kernel suite for benchmarking wireless systems.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

Data storage time sensitive ECC schemes for MLC NAND Flash memories.
Proceedings of the IEEE International Conference on Acoustics, 2013

A speech emotion recognition framework based on latent Dirichlet allocation: Algorithm and FPGA implementation.
Proceedings of the IEEE International Conference on Acoustics, 2013

Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Compact modeling of STT-MTJ for SPICE simulation.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Parallel High Throughput Soft-Output Sphere Decoding Algorithm.
J. Signal Process. Syst., 2012

Quality-Aware Techniques for Reducing Power of JPEG Codecs.
J. Signal Process. Syst., 2012

Product Code Schemes for Error Correction in MLC NAND Flash Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.
IEEE J. Solid State Circuits, 2012

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding.
EURASIP J. Adv. Signal Process., 2012

Reducing the Complexity of Orthogonal Code Based Synthetic Aperture Ultrasound System.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A top-down design methodology using virtual platforms for concept development.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

An analytical approach to efficient circuit variability analysis in scaled CMOS design.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Transpose-free SAR imaging on FPGA platform.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design of orthogonal coded excitation for synthetic aperture imaging in ultrasound systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Hierarchical modeling of Phase Change memory for reliable design.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Neural activity tracking using spatial compressive particle filtering.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Lifelogging: Archival and retrieval of continuously recorded audio using wearable devices.
Proceedings of the 2012 IEEE International Conference on Emerging Signal Processing Applications, 2012

Process variation in near-threshold wide SIMD architectures.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Accelerating neuromorphic vision algorithms for recognition.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

EEG/MEG artifact suppression for improved neural activity estimation.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data.
J. Signal Process. Syst., 2011

Algorithm and Parallel Implementation of Particle Filtering and its Use in Waveform-Agile Sensing.
J. Signal Process. Syst., 2011

Accurate Area, Time and Power Models for FPGA-Based Implementations.
J. Signal Process. Syst., 2011

Multidimensional DFT IP Generator for FPGA Platforms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Flexible product code-based ECC schemes for MLC NAND Flash memories.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Real-time closed-loop tracking of an unknown number of neural sources using probability hypothesis density particle filtering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A hardware architecture for accelerating neuromorphic vision algorithms.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A framework for accelerating neuromorphic-vision algorithms on FPGAs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Energy-optimized high performance FFT processor.
Proceedings of the IEEE International Conference on Acoustics, 2011

Data-path and memory error compensation technique for low power JPEG implementation.
Proceedings of the IEEE International Conference on Acoustics, 2011

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design.
Proceedings of the 48th Design Automation Conference, 2011

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs.
Proceedings of the 48th Design Automation Conference, 2011

Low energy motion estimation via selective aproximations.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

FPGA-accelerator system for computing biologically inspired feature extraction models.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
A Low-Power DSP for Wireless Communications.
IEEE Trans. Very Large Scale Integr. Syst., 2010

AnySP: Anytime Anywhere Anyway Signal Processing.
IEEE Micro, 2010

Mobile Supercomputers for the Next-Generation Cell Phone.
Computer, 2010

Diet SODA: a power-efficient processor for digital cameras.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Bandwidth-intensive FPGA architecture for multi-dimensional DFT.
Proceedings of the IEEE International Conference on Acoustics, 2010

A distributed psycho-visually motivated Canny edge detector.
Proceedings of the IEEE International Conference on Acoustics, 2010

Energy-aware adaptive OFDM systems.
Proceedings of the IEEE International Conference on Acoustics, 2010

A special-purpose compiler for look-up table and code generation for function evaluation.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Energy-Efficient Video Transmission Over a Wireless Link.
IEEE Trans. Veh. Technol., 2009

Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Architecture-aware LDPC code design for multiprocessor software defined radio systems.
IEEE Trans. Signal Process., 2009

Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.
IEEE Trans. Computers, 2009

Customizing wide-SIMD architectures for H.264.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Low power robust signal processing.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities.
Proceedings of the International Conference on Image Processing, 2009

Energy-aware error control coding for Flash memories.
Proceedings of the 46th Design Automation Conference, 2009

2008
A fuel-cell-battery hybrid for portable embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2008

Energy-efficient dynamic task scheduling algorithms for DVS systems.
ACM Trans. Embed. Comput. Syst., 2008

Efficient mapping of advanced signal processing algorithms on multi-processor architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Efficient image reconstruction using partial 2D Fourier transform.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

A parameterized dataflow language extension for embedded streaming systems.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

From SODA to scotch: The evolution of a wireless baseband processor.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Extending the lifetime of media recorders constrained by battery and flash memory size.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Accurate models for estimating area and power of FPGA implementations.
Proceedings of the IEEE International Conference on Acoustics, 2008

2007
Automatic antenna-tuning unit for software-defined and cognitive radio.
Wirel. Commun. Mob. Comput., 2007

A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends.
IEEE Trans. Very Large Scale Integr. Syst., 2007

SODA: A High-Performance DSP Architecture for Software-Defined Radio.
IEEE Micro, 2007

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Design and Analysis of LDPC Decoders for Software Defined Radio.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Sphere Decoding for Multiprocessor Architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

The Next Generation Challenge for Software Defined Radio.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Throughput of multi-core processors under thermal constraints.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Memory Efficient LDPC Code Design for High Throughput Software Defined Radio (SDR) systems.
Proceedings of the IEEE International Conference on Acoustics, 2007

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
Proceedings of the FPL 2007, 2007

Dynamic Power Management with Hybrid Power Sources.
Proceedings of the 44th Design Automation Conference, 2007

2006
A Survey on Lifting-based Discrete Wavelet Transform Architectures.
J. VLSI Signal Process., 2006

Study of energy and performance of space-time decoding systems in concatenation with turbo decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A coprocessor architecture for fast protein structure prediction.
Pattern Recognit., 2006

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Architecture-Aware LDPC Code Design for Software Defined Radio.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Design and Implementation of Turbo Decoders for Software Defined Radio.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An optimal analytical solution for processor speed control with thermal constraints.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Reducing idle mode power in software defined radio terminals.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

SODA: A Low-power Architecture For Software Radio.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Aggregated Circulant Matrix Based LDPC Codes.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Extending the lifetime of fuel cell based hybrid systems.
Proceedings of the 43rd Design Automation Conference, 2006

High-level power management of embedded systems with application-specific energy cost functions.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Memory sub-banking scheme for high throughput MAP-based SISO decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Static task-scheduling algorithms for battery-powered DVS systems.
IEEE Trans. Very Large Scale Integr. Syst., 2005

An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

System-level energy-efficient dynamic task scheduling.
Proceedings of the 42nd Design Automation Conference, 2005

An efficient dynamic task scheduling algorithm for battery powered DVS systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Unified Bayesian Decision Theory Perspective to Sensor Networks.
Proceedings of the Intelligent Control, 2005

2004
Design and implementation of low-energy turbo decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2004

An approach for adaptively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes.
IEEE Trans. Signal Process., 2004

Multi-Module Multi-Port Memory Design for Low Power Embedded Systems.
Des. Autom. Embed. Syst., 2004

Mobile Supercomputers.
Computer, 2004

Optimum Buffer Size for Dynamic Voltage Processors.
Proceedings of the Integrated Circuit and System Design, 2004

A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Parameterized SoC design for portable systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A dynamic task scheduling algorithm for battery powered DVS systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Memory sub-banking scheme for high throughput turbo decoder.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Variable voltage task scheduling algorithms for minimizing energy/power.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A high-performance JPEG2000 architecture.
IEEE Trans. Circuits Syst. Video Technol., 2003

2002
A low power scheduling scheme with resources operating at multiple voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2002

A VLSI architecture for lifting-based forward and inverse wavelet transform.
IEEE Trans. Signal Process., 2002

Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Architectural approaches to reduce leakage energy in caches.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Energy-efficient turbo decoder.
Proceedings of the IEEE International Conference on Acoustics, 2002

Battery-conscious task sequencing for portable devices including voltage/clock scaling.
Proceedings of the 39th Design Automation Conference, 2002

2001
Data memory design and exploration for low-power embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

Variable voltage task scheduling algorithms for minimizing energy.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Voltage Scaling for Energy Minimization with QoS Constraints.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An approach for enabling DCT/IDCT energy reduction scalability in MPEG-2 video codecs.
Proceedings of the IEEE International Conference on Acoustics, 2001

Efficient implementation of a set of lifting based wavelet filters.
Proceedings of the IEEE International Conference on Acoustics, 2001

Address Code Generation for Digital Signal Processors.
Proceedings of the 38th Design Automation Conference, 2001

2000
VLSI architectures for weighted order statistic (WOS) filters.
Signal Process., 2000

Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Energy-efficient code generation for DSP56000 family (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

ILP-based scheme for low power scheduling and resource binding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A programmable processor for cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Multi-Bit Binary Arithmetic Coding Technique.
Proceedings of the 2000 International Conference on Image Processing, 2000

Variable voltage task scheduling for minimizing energy or minimizing power.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Memory exploration for low power embedded systems.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Instruction level power model of microcontrollers.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A DWT-based encoder architecture for symmetrically extended images.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Activity models for use in low power, high-level synthesis.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1997
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Architectures for wavelet transforms: A survey.
J. VLSI Signal Process., 1996

A new architecture for the Viterbi decoder for code rate k/n.
IEEE Trans. Commun., 1996

Motion estimation of two-dimensional objects based on the straight line hough transform: A new approach.
Pattern Recognit., 1996

Efficient realizations of analysis and synthesis filters based on the 2-D discrete wavelet transform.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995
Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers.
IEEE Trans. Signal Process., 1995

A digit-serial architecture for gray-scale morphological filtering.
IEEE Trans. Image Process., 1995

Architectures for hierarchical and other block matching algorithms.
IEEE Trans. Circuits Syst. Video Technol., 1995

A New Architecture for the Viterbi Decoder for Code Rate k/n1.
IEEE Trans. Commun., 1995

A New Viterbi Decoder Design for Code Rate <i>K/N</i>.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Low power data format converter design using semi-static register allocation.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A new Viterbi decoder design for code rate k/n.
Proceedings of the 1995 International Conference on Acoustics, 1995

A survey of architectures for the discrete and continuous wavelet transforms.
Proceedings of the 1995 International Conference on Acoustics, 1995

1994
Novel sorting network-based architectures for rank order filters.
IEEE Trans. Very Large Scale Integr. Syst., 1994

A comment on 'on prime factor mapping for the discrete Hartley transform'.
IEEE Trans. Signal Process., 1994

High sample rate array architectures for median filters.
IEEE Trans. Signal Process., 1994

High Sample Rate Architectures for Block Adaptive Filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

VLSI Architectures for Hierarchical Block Matching.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Novel Sorting Netowrk-Based Architectures for Rank Order Filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Efficient Architectures for Hidden Surface Removal.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

1993
Comments on 'Highly modular systolic structures for denominator-separable 2-D recursive filters' [and reply].
IEEE Trans. Signal Process., 1993

Efficient stack filter implementations of rank order filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

VLSI architectures for recursive median filters.
Proceedings of the IEEE International Conference on Acoustics, 1993

1991
VLSI Architectures for Multidimensional Transforms.
IEEE Trans. Computers, 1991

1990
VLSI Architectures for Real-Time Signal Processing.
PhD thesis, 1990

Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition.
IEEE Trans. Computers, 1990

A parallel algorithm for template matching on an SIMD mesh connected computer.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990


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