Meng Li

Orcid: 0000-0002-7212-2264

Affiliations:
  • Peking University, Beijing, China
  • Meta / Facebook (former)
  • University of Texas at Austin, Department of Electrical and Computer Engineering, TX, USA (former)


According to our database1, Meng Li authored at least 79 papers between 2015 and 2024.

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Bibliography

2024
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

HEQuant: Marrying Homomorphic Encryption and Quantization for Communication-Efficient Private Inference.
CoRR, 2024

2023
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference.
CoRR, 2023

EBSR: Enhanced Binary Neural Network for Image Super-Resolution.
CoRR, 2023

MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
PathFusion: Path-consistent Lidar-Camera Deep Feature Fusion.
CoRR, 2022

MPCViT: Searching for MPC-friendly Vision Transformer with Heterogeneous Attention.
CoRR, 2022

BiT: Robustly Binarized Multi-distilled Transformer.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Decentralized Unsupervised Learning of Visual Representations.
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

DepthShrinker: A New Compression Paradigm Towards Boosting Real-Hardware Efficiency of Compact Neural Networks.
Proceedings of the International Conference on Machine Learning, 2022

NASViT: Neural Architecture Search for Efficient Vision Transformers with Gradient Conflict aware Supernet Training.
Proceedings of the Tenth International Conference on Learning Representations, 2022

Omni-Sparsity DNN: Fast Sparsity Optimization for On-Device Streaming E2E ASR Via Supernet.
Proceedings of the IEEE International Conference on Acoustics, 2022

Contrastive quant: quantization makes stronger contrastive learning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

SplitNets: Designing Neural Architectures for Efficient Distributed Computing on Head-Mounted Systems.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

ScaleNAS: Multi-Path One-Shot NAS for Scale-Aware High-Resolution Representation.
Proceedings of the International Conference on Automated Machine Learning, 2022

2021
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Distributed Unsupervised Visual Representation Learning with Fused Features.
CoRR, 2021

Low-Rank+Sparse Tensor Compression for Neural Networks.
CoRR, 2021

Noisy Training Improves E2E ASR for the Edge.
CoRR, 2021

Improve Vision Transformers Training by Suppressing Over-smoothing.
CoRR, 2021

AlphaNet: Improved Training of Supernet with Alpha-Divergence.
CoRR, 2021

PyTorchVideo: A Deep Learning Library for Video Understanding.
Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021

DIAN: Differentiable Accelerator-Network Co-Search Towards Maximal DNN Efficiency.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

AlphaNet: Improved Training of Supernets with Alpha-Divergence.
Proceedings of the 38th International Conference on Machine Learning, 2021

Double-Win Quant: Aggressively Winning Robustness of Quantized Deep Neural Networks via Random Precision Training and Inference.
Proceedings of the 38th International Conference on Machine Learning, 2021

CPT: Efficient Deep Neural Network Training via Cyclic Precision.
Proceedings of the 9th International Conference on Learning Representations, 2021

AttentiveNAS: Improving Neural Architecture Search via Attentive Sampling.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

KeepAugment: A Simple Information-Preserving Data Augmentation Approach.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

NASGEM: Neural Architecture Search via Graph Embedding Method.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ScaleNAS: One-Shot Learning of Scale-Aware Representations for Visual Recognition.
CoRR, 2020

DNA: Differentiable Network-Accelerator Co-Search.
CoRR, 2020

NASGEM: Neural Architecture Search via Graph Embedding Method.
CoRR, 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020

Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization.
CoRR, 2020

RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview.
ACM Trans. Design Autom. Electr. Syst., 2019

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.
IEEE Trans. Inf. Forensics Secur., 2019

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Provably Secure Camouflaging Strategy for IC Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Energy-Aware Neural Architecture Optimization with Fast Splitting Steepest Descent.
CoRR, 2019

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Hardware-software co-design of slimmed optical neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

LithoROC: lithography hotspot detection with explicit ROC optimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst., 2018

Subresolution Assist Feature Generation With Supervised Data Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SD-PUF: Spliced Digital Physical Unclonable Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Federated Learning with Non-IID Data.
CoRR, 2018

TimingSAT: Decamouflaging Timing-based Logic Obfuscation.
Proceedings of the IEEE International Test Conference, 2018

Power Grid Reduction by Sparse Convex Optimization.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Layout-dependent aging mitigation for critical path timing.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Redundant Local-Loop Insertion for Unidirectional Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.
CoRR, 2017

UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AppSAT: Approximately deobfuscating integrated circuits.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
LRR-DPUF: learning resilient and reliable digital physical unclonable function.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A Monte Carlo simulation flow for SEU analysis of sequential circuits.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Practical public PUF enabled by solving max-flow problem on chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Novel power grid reduction method based on L1 regularization.
Proceedings of the 52nd Annual Design Automation Conference, 2015


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