G. Edward Suh

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

SecNDP: Secure Near-Data Processing with Untrusted Memory.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Sinan: Data Driven Resource Management for Cloud Microservices.

[BibT_eX]

[DOI]

CoRR, 2021

Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices.

[BibT_eX]

[DOI]

CoRR, 2021

Guessing Outputs of Dynamically Pruned CNNs Using Memory Access Patterns.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Wireless Charging Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Alexander S. La Cour

Khurram K. Afridi

Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021

Sinan: ML-based and QoS-aware resource management for cloud microservices.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

BCD deduplication: effective memory compression using partial cache-line deduplication.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

Path Planning Under Malicious Injections and Removals of Perceived Obstacles: A Probabilistic Programming Approach.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2020

The Cost of Software-Based Memory Management Without Virtual Memory.

[BibT_eX]

[DOI]

Drew Zagieboylo

Andrew C. Myers

CoRR, 2020

GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2020

MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration.

[BibT_eX]

[DOI]

CoRR, 2020

A Case for Maximal Leakage as a Side Channel Leakage Metric.

[BibT_eX]

[DOI]

Benjamin Wu

Aaron B. Wagner

CoRR, 2020

Stealthy Tracking of Autonomous Vehicles with Cache Side Channels.

[BibT_eX]

[DOI]

Mulong Luo

Andrew C. Myers

Proceedings of the 29th USENIX Security Symposium, 2020

Strong Asymptotic Composition Theorems for Sibson Mutual Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2020

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

Optimal Mechanisms Under Maximal Leakage.

[BibT_eX]

[DOI]

Benjamin Wu

Aaron B. Wagner

Proceedings of the 8th IEEE Conference on Communications and Network Security, 2020

Efficient nursery sizing for managed languages on multi-core processors with shared caches.

[BibT_eX]

[DOI]

Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020

2019

Channel Gating Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

TWiCe: preventing row-hammering by exploiting time window counters.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Using Information Flow to Design an ISA that Controls Timing Channels.

[BibT_eX]

[DOI]

Drew Zagieboylo

Andrew C. Myers

Proceedings of the 32nd IEEE Computer Security Foundations Symposium, 2019

2018

Channel Gating Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

FPGA-Based Remote Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Mark Zhao

Proceedings of the 2018 IEEE Symposium on Security and Privacy, 2018

An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Hardware-software co-optimization of memory management in dynamic languages.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management, 2018

Quantitative Overhead Analysis for Python.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

High-level synthesis with timing-sensitive information flow enforcement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Reverse engineering convolutional neural networks through side-channel information leaks.

[BibT_eX]

[DOI]

Weizhe Hua

Zhiru Zhang

Proceedings of the 55th Annual Design Automation Conference, 2018

Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control.

[BibT_eX]

[DOI]

Proceedings of the 2018 Workshop on Cyber-Physical Systems Security and PrivaCy, 2018

HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

2017

Secure Dynamic Memory Scheduling Against Timing Channel Attacks.

[BibT_eX]

[DOI]

Yao Wang

Benjamin Wu

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Secure Information Flow Verification with Mutable Dependent Types.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Efficient data supply for hardware accelerators with prefetching and access/execute decoupling.

[BibT_eX]

[DOI]

Tao Chen

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation.

[BibT_eX]

[DOI]

Taejoon Song

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

SecDCP: secure dynamic cache partitioning for efficient timing channel protection.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Prediction-guided performance-energy trade-off for interactive applications.

[BibT_eX]

[DOI]

Taejoon Song

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Execution time prediction for energy-efficient hardware accelerators.

[BibT_eX]

[DOI]

Tao Chen

Alexander Rucker

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Run-time monitoring with adjustable overhead using dataflow-guided filtering.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Improving worst-case cache performance through selective bypassing and register-indexed cache.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

A Hardware Design Language for Timing-Sensitive Information-Flow Security.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Slack-aware opportunistic monitoring for real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Author retrospective for analytical cache models with applications to cache partitioning.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing.

[BibT_eX]

[DOI]

Christopher W. Fletcher

Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Timing channel protection for a shared memory controller.

[BibT_eX]

[DOI]

Yao Wang

Andrew Ferraiuolo

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Low-overhead and high coverage run-time race detection through selective meta-data management.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Optimal and Heuristic Application-Aware Oblivious Routing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Hiding Information in Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Symposium on Security and Privacy, 2013

Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Non-race concurrency bug detection through order-sensitive critical sections.

[BibT_eX]

[DOI]

Ruirui C. Huang

Erik Halberg

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Security and Privacy, 2012

Efficient Timing Channel Protection for On-Chip Networks.

[BibT_eX]

[DOI]

Yao Wang

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

High-performance parallel accelerator for flexible and efficient run-time monitoring.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

Worst-case execution time analysis for parallel run-time monitoring.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

On the performance of averaged optimal routing.

[BibT_eX]

[DOI]

Nithin Michael

Ao Tang

Proceedings of the 46th Annual Conference on Information Sciences and Systems, 2012

Hardware enhanced security.

[BibT_eX]

[DOI]

Ruby B. Lee

Simha Sethumadhavan

Proceedings of the ACM Conference on Computer and Communications Security, 2012

2011

Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations.

[BibT_eX]

[DOI]

Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011

Systematic Security Assessment at an Early Processor Design Stage.

[BibT_eX]

[DOI]

Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011

Analysis of application-aware on-chip routing under traffic uncertainty.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Precise exception support for decoupled run-time monitoring architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric.

[BibT_eX]

[DOI]

Greg Malysa

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A non-volatile microcontroller with integrated floating-gate transistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

2010

Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and Emulations.

[BibT_eX]

[DOI]

Andrew H. Chan

Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

IVEC: off-chip memory integrity protection for both security and reliability.

[BibT_eX]

[DOI]

Ruirui C. Huang

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Orthrus: efficient software integrity protection on multi-cores.

[BibT_eX]

[DOI]

Ruirui C. Huang

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

Static virtual channel allocation in oblivious routing.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Application-aware deadlock-free oblivious routing.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Hardware authentication leveraging performance limits in detailed simulations and emulations.

[BibT_eX]

[DOI]

Andrew H. Chan

Proceedings of the 46th Design Automation Conference, 2009

2008

Diastolic arrays: throughput-driven reconfigurable computing.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Physical Unclonable Functions for Device Authentication and Secret Key Generation.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Speeding up Exponentiation using an Untrusted Computational Resource.

[BibT_eX]

[DOI]

Des. Codes Cryptogr., 2006

2005

AEGIS: a single-chip secure processor.

[BibT_eX]

[DOI]

PhD thesis, 2005

Extracting secret keys from integrated circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

AEGIS: A single-chip secure processor.

[BibT_eX]

[DOI]

Charles W. O'Donnell

Inf. Secur. Tech. Rep., 2005

Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Symposium on Security and Privacy (S&P 2005), 2005

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.

[BibT_eX]

[DOI]

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004

Dynamic Partitioning of Shared Cache Memory.

[BibT_eX]

[DOI]

Larry Rudolph

J. Supercomput., 2004

Secure program execution via dynamic information flow tracking.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003

Efficient Memory Integrity Verification and Encryption for Secure Processors.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

AEGIS: architecture for tamper-evident and tamper-resistant processing.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Caches and Hash Trees for Efficient Memory Integrity Verification.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Embedded intelligent SRAM.

[BibT_eX]

[DOI]

Prabhat Jain

Proceedings of the 40th Design Automation Conference, 2003

Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking.

[BibT_eX]

[DOI]

Proceedings of the Advances in Cryptology - ASIACRYPT 2003, 9th International Conference on the Theory and Application of Cryptology and Information Security, Taipei, Taiwan, November 30, 2003

2002

A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning.

[BibT_eX]

[DOI]