Zoltán Nagy

Orcid: 0000-0002-0992-7123

Affiliations:
  • Hungarian Academy of Sciences, Institute for Computer Science and Control, Budapest, Hungary
  • Péter Pázmány Catholic University, Budapest, Hungary
  • University of Veszprém, Hungary (former)


According to our database1, Zoltán Nagy authored at least 38 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2022
Hybrid FPGA-CPU-Based Architecture for Object Recognition in Visual Servoing of Arm Prosthesis.
J. Imaging, 2022

2021
Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA.
IEEE Trans. Biomed. Eng., 2021

Implementation of Scale Invariant Feature Transform detector on FPGA for low-power wearable devices for prostheses control.
Int. J. Circuit Theory Appl., 2021

2019
FPGA-based SIFT implementation for wearable computing.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2017
FPGA-based neural probe positioning to improve spike sorting with OSort algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA-based real-time multichannel neural dataset generation.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Fast evaluation of magnetic fields with multipole method implemented on FPGA.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
A real-time multi-camera vision system for UAV collision warning and navigation.
J. Real Time Image Process., 2016

2015
Cellular sensor-processor array based visual collision warning sensor.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of parallel processor architectures for the solution of the Black-Scholes PDE.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Emulating massively parallel non-Boolean operators on FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
The density matrix renormalization group algorithm on kilo-processor architectures: Implementation and trade-offs.
Comput. Phys. Commun., 2014

Accelerating unstructured finite volume computations on field-programmable gate arrays.
Concurr. Comput. Pract. Exp., 2014

2013
A Five-Camera Vision System for UAV Visual Attitude Calculation and Collision Warning.
Proceedings of the Computer Vision Systems - 9th International Conference, 2013

Implementation trade-offs of the density matrix renormalization group algorithm on kilo-processor architectures.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

FPGA-implementation of a holographic pattern-matching algorithm.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Analysis of myoelectric signals using a Field Programmable SoC.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Volume and power optimized high-performance system for UAV collision avoidance.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA.
J. Signal Process. Syst., 2011

Efficient mapping of mathematical expressions to FPGAs: Exploring different design methodologies.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2009
Simulation of 2D inviscid, adiabatic, compressible flows on emulated digital CNN-UM.
Int. J. Circuit Theory Appl., 2009

FPGA-Based Real Time, Multichannel Emulated-Digital Retina Model Implementation.
EURASIP J. Adv. Signal Process., 2009

Simulation of Two-Dimensional Supersonic Flows on Emulated-Digital CNN-UM.
EURASIP J. Adv. Signal Process., 2009

Supersonic Flow Simulation on IBM Cell Processor based Emulated Digital Cellular Neural Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Computational fluid flow simulation on body fitted mesh geometry with IBM cell broadband engine architecture.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Implementation of a parallel SAD based wavefront sensor architecture on FPGA.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Emulált digitális CNN-UM architektúra megvalósítása újrakonfigurálható áramkörökön és alkalmazásai
PhD thesis, 2008

Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application.
Int. J. Circuit Theory Appl., 2008

Toward exploitation of cell multi-processor array in time-consuming applications by using CNN model.
Int. J. Circuit Theory Appl., 2008

Exploitation of Cell Multi-Processor Array in Solution of Spatio-Temporal Dynamics.
ERCIM News, 2008

Supersonic Flow Simulation on Emulated Digital Cellular Neural Networks.
ERCIM News, 2008

2007
CNN-UM based transversely isotropic elastic wave propagation simulation.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

CNN model on cell multiprocessor array.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Emulated digital CNN solution for two dimensional compressible flows.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Emulated digital CNN-UM solution of partial differential equations.
Int. J. Circuit Theory Appl., 2006

An advanced emulated digital retina model on FPGA to implement a real-time test environment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2002
Configurable multi-layer CNN-UM emulator on FPGA using distributed arithmetic.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002


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