Ahmed S. Emara

Orcid: 0000-0002-7329-7795

According to our database1, Ahmed S. Emara authored at least 13 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Error Detection and Masking Circuit with High Diagnosability for Redundant Sensors.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2021
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
Optimized Periodic ΣΔ Bitstreams for DC Signal Generation Used in Dynamic Calibration Applications.
IEEE Open J. Circuits Syst., 2020

Using Optimized Butterworth-Based ΣΔ Bitstreams for the Testing of High-Resolution Data Converters.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019
Selecting the Fastest Settling-Time Filter in PDM-based DACs used for Dynamic Calibration Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

On the Design of DACs for Dynamic Calibration Applications using Periodic Sequences from ΣΔ Modulators.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2016
Evaluation of multi-level buck converters for low-power applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Effect of open faults in FPGA switch matrices on fault detection mechanisms.
Proceedings of the 28th International Conference on Microelectronics, 2016

Testing of memristor ratioed logic (MRL) XOR gate.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
High coverage test for the second generation current conveyor.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Design and analysis of memristor-based min-max circuit.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Memristor-based Center-Of-Gravity (COG) defuzzifier circuit.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Testing current mode two-input logic gates.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014


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