Akhil Raj Baranwal

According to our database, Akhil Raj Baranwal authored at least 6 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

HiSpMM: High Performance High Bandwidth Sparse-Dense Matrix Multiplication on HBM-equipped FPGAs.

Ahmad Sedigh Baroughi, Manoj B. Rajashekar, Akhil Raj Baranwal, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., March, 2026

2025

MAD-HiSpMV: Matrix Adaptive Design with Hybrid Row Distribution for Imbalanced SpMV Acceleration on FPGAs.

Manoj B. Rajashekar, Akhil Raj Baranwal, Xingyu Tian, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., December, 2025

PoCo: Extending Task-Parallel HLS Programming with Shared Multi-<i>P</i>r<i>o</i>ducer Multi-<i>Co</i>nsumer Buffer Support.

Akhil Raj Baranwal, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., December, 2025

2024

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.

Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., September, 2024

2021

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.

Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

<i>MemOReL</i>: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems.

Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021