Siva Satyendra Sahoo

According to our database, Siva Satyendra Sahoo authored at least 28 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories.

Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

IEEE Embed. Syst. Lett., December, 2023

<i>AxOTreeS</i>: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators.

Siva Satyendra Sahoo, Salim Ullah, Akash Kumar

ACM Trans. Embed. Comput. Syst., October, 2023

AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming.

Siva Satyendra Sahoo, Salim Ullah, Akash Kumar

CoRR, 2023

AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling.

Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar

CoRR, 2023

CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators.

Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks.

Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

<i>AppAxO</i>: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems.

Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar

ACM Trans. Embed. Comput. Syst., 2022

BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems.

Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML.

Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.

Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures.

Salim Ullah, Hendrik Schmidl, Siva Satyendra Sahoo, Semeen Rehman, Akash Kumar

IEEE Trans. Computers, 2021

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.

Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar

IEEE Access, 2021

Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.

Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems.

Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

<i>MemOReL</i>: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems.

Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem.

Behnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems.

Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives.

Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel Chang Bing Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh

Proceedings of the CODES/ISSS 2021, 2021

2020

Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems.

Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.

Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems.

Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems.

Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar

Integr., 2019

A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems.

Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems.

Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning.

Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the International Conference on Field-Programmable Technology, 2018

Lifetime-aware design methodology for dynamic partially reconfigurable systems.

Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2016

Cross-layer fault-tolerant design of real-time systems.

Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults.

Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016