Yuze Chi

Orcid: 0000-0002-5885-0425

According to our database1, Yuze Chi authored at least 34 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.
CoRR, 2023

Democratizing Domain-Specific Computing.
Commun. ACM, 2023

Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators.
Proceedings of the IEEE International Conference on Acoustics, 2022

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

RapidStream: Parallel Physical Implementation of FPGA HLS Designs.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Accelerating SSSP for Power-Law Graphs.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Design Automation and Optimization for Memory-Bound Application Accelerators.
PhD thesis, 2021

SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation.
CoRR, 2021

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

HBM Connect: High-Performance HLS Interconnect for FPGA HBM.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
FLASH: Fast, Parallel, and Accurate Simulator for HLS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization.
CoRR, 2020

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Exploiting Computation Reuse for Stencil Accelerators.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Rapid Cycle-Accurate Simulator for High-Level Synthesis.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
SODA: stencil with optimized dataflow architecture.
Proceedings of the International Conference on Computer-Aided Design, 2018

An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
NXgraph: An efficient graph processing system on a single machine.
Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016


  Loading...