Akiyo Nomura

Orcid: 0000-0003-2354-867X

According to our database1, Akiyo Nomura authored at least 9 papers between 2018 and 2023.

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Bibliography

2023
An analog-AI chip for energy-efficient speech recognition and transcription.
Nat., 2023

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Pattern Training, Inference, and Regeneration Demonstration Using On-Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine.
Adv. Intell. Syst., 2022

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method.
Neural Process. Lett., 2021

2019
Training Large-Scale Spiking Neural Networks on Multi-core Neuromorphic System Using Backpropagation.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

2018
NVM Weight Variation Impact on Analog Spiking Neural Network Chip.
Proceedings of the Neural Information Processing - 25th International Conference, 2018


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