Stefano Ambrogio

Orcid: 0000-0002-5475-4209

According to our database¹, Stefano Ambrogio authored at least 29 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2024

Roadmap to Neuromorphic Computing with Emerging Technologies.

[BibT_eX]

[DOI]

Teresa Serrano-Gotarredona

Bernabé Linares-Barranco

Christian Monzio Compagnoni

Frank Brückerhoff-Plückelmann

Wolfram H. P. Pernice

Sayeed Shafayet Chowdhury

CoRR, 2024

VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation.

[BibT_eX]

[DOI]

Prashanth Vijayaraghavan

CoRR, 2024

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization.

[BibT_eX]

[DOI]

Prashanth Vijayaraghavan

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

2023

An analog-AI chip for energy-efficient speech recognition and transcription.

[BibT_eX]

[DOI]

Nat., 2023

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.

[BibT_eX]

[DOI]

Frontiers Comput. Neurosci., 2021

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Optimization of Analog Accelerators for Deep Neural Networks Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Accelerating Deep Neural Networks with Analog Memory Devices.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2019

Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Equivalent-accuracy accelerated neural-network training using analogue memory.

[BibT_eX]

[DOI]

Nat., 2018

Stochastic Learning in Neuromorphic Hardware via Spike Timing Dependent Plasticity With RRAM Synapses.

[BibT_eX]

[DOI]

Alessandro S. Spinelli

Daniele Ielmini

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neuromorphic devices and architectures for next-generation cognitive computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016

Modeling of reliability and neuromorphic application of resistive switching devices.

[BibT_eX]

[DOI]

Stefano Ambrogio

PhD thesis, 2016

Neuromorphic computing with hybrid memristive/CMOS synapses for real-time learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

True Random Number Generation by Variability of Resistive Switching in Oxide-Based Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Understanding pulsed-cycling variability and endurance in HfOx RRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Data retention statistics and modelling in HfO2 resistive switching memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

Statistical modeling of program and read variability in resistive switching devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Analytical modelling and leakage optimization in complementary resistive switch (CRS) crossbar arrays.

[BibT_eX]

[DOI]

Proceedings of the 44th European Solid State Device Research Conference, 2014

Stefano Ambrogio

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