Irem Boybat

Orcid: 0000-0002-4255-8622

According to our database1, Irem Boybat authored at least 40 papers between 2013 and 2024.

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Bibliography

2024
LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles.
CoRR, 2024

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023

ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.
IEEE Trans. Computers, July, 2023

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023

AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars.
Neuromorph. Comput. Eng., 2022

ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator.
IEEE Micro, 2022

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Benchmarking energy consumption and latency for neuromorphic computing in condensed matter and particle physics.
CoRR, 2022

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator.
CoRR, 2021

Accurate Weight Mapping in a Multi-Memristive Synaptic Unit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021



End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020

Mixed-precision deep learning based on computational memory.
CoRR, 2020

Accurate Emulation of Memristive Crossbar Arrays for In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Deep learning acceleration based on in-memory computing.
IBM J. Res. Dev., 2019

Accurate deep neural network inference using computational phase-change memory.
CoRR, 2019

Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses.
CoRR, 2019

Computational memory-based inference and training of deep neural networks.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Multi-ReRAM Synapses for Artificial Neural Network Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Phase-Change Memory Models for Deep Learning Training and Inference.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Equivalent-accuracy accelerated neural-network training using analogue memory.
Nat., 2018

Impact of conductance drift on multi-PCM synaptic architectures.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018

Mixed-precision architecture based on computational memory for training deep neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Mixed-precision training of deep neural networks using computational memory.
CoRR, 2017

Neuromorphic computing with multi-memristive synapses.
CoRR, 2017

An efficient synaptic architecture for artificial neural networks.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017

Fatiguing STDP: Learning from spike-timing codes in the presence of rate codes.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2013
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013


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