Wilfried Haensch

Orcid: 0000-0003-1725-7171

According to our database1, Wilfried Haensch authored at least 30 papers between 2006 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to metal?oxide?semiconductor field-effect transistor device physics and scaling".

Timeline

Legend:

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Online presence:

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Bibliography

2024
Multi-Function Multi-Way Analog Technology for Sustainable Machine Intelligence Computation.
CoRR, 2024

2023
LRMP: Layer Replication with Mixed Precision for Spatial In-memory DNN Accelerators.
CoRR, 2023

2022
Neural Network Training With Asymmetric Crosspoint Elements.
Frontiers Artif. Intell., 2022

A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks.
CoRR, 2022

2021
Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method.
Neural Process. Lett., 2021

2020
Training Large-scale Artificial Neural Networks on Simulated Resistive Crossbar Arrays.
IEEE Des. Test, 2020

2019
The Next Generation of Deep Learning Hardware: Analog Computing.
Proc. IEEE, 2019

Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev., 2019

Algorithm for Training Neural Networks on Resistive Device Arrays.
CoRR, 2019

Training large-scale ANNs on simulated resistive crossbar arrays.
CoRR, 2019


Training Large-Scale Spiking Neural Networks on Multi-core Neuromorphic System Using Backpropagation.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

2018
Efficient ConvNets for Analog Arrays.
CoRR, 2018

Training LSTM Networks with Resistive Cross-Point Devices.
CoRR, 2018

NVM Weight Variation Impact on Analog Spiking Neural Network Chip.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

2017
Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices.
CoRR, 2017

Analog CMOS-based resistive processing unit for deep neural network training.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017


2016

2012
Near-threshold operation for power-efficient computing?: it depends...
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Practical Strategies for Power-Efficient Computing Technologies.
Proc. IEEE, 2010

2008
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.
IEEE J. Solid State Circuits, 2008

Why should we do 3D integration?
Proceedings of the 45th Design Automation Conference, 2008

2007
Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Proceedings of the 44th Design Automation Conference, 2007

2006
Ultralow-voltage, minimum-energy CMOS.
IBM J. Res. Dev., 2006

Silicon CMOS devices beyond scaling.
IBM J. Res. Dev., 2006

Preface.
IBM J. Res. Dev., 2006

Optimizing CMOS technology for maximum performance.
IBM J. Res. Dev., 2006

High-performance CMOS variability in the 65-nm regime and beyond.
IBM J. Res. Dev., 2006


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