Alejandro Arteaga

According to our database, Alejandro Arteaga authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Performance Analysis of Convolution Function for IA Edge Computing Acceleration Using a 32-bit RISC-V CPU Implementation.

David Cantero, Alexander Ugena, Laura Sanz, Alejandro Arteaga, Armando Astarloa

Proceedings of the 40th Conference on Design of Circuits and Integrated Systems, 2025

A Proof-Of-Concept ASIC RISC-V Based SoC for Industrial Applications.

Sara Alonso, Alejandro Arteaga, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, Jose Ignacio Garate, José Ángel Araujo, Victor Martínez, Unai Bidarte, Armando Astarloa

Proceedings of the 40th Conference on Design of Circuits and Integrated Systems, 2025

2024

Smart Carrier for Scan Chain Emulation of ASIC Prototypes under Test.

Juan Manuel Galán, Ainhoa Cortés, Andoni Irizar, Alejandro Arteaga, Jose Ignacio Garate, Armando Astarloa

Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024