Jesús Lázaro

Orcid: 0000-0002-7483-3609

Affiliations:
  • University of the Basque Country, Bilbao, Spain


According to our database1, Jesús Lázaro authored at least 66 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems.
IEEE Trans. Reliab., March, 2024

High Performance Platform to Detect Faults in the Smart Grid by Artificial Intelligence Inference.
IEEE Trans. Smart Grid, January, 2024

2023
Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Embedded firewall for on-chip bus transactions.
Comput. Electr. Eng., 2022

High-Performance Computing Architecture for Sample Value Processing in the Smart Grid.
IEEE Access, 2022

Design and development of an IoT device provided with a voice interface to improve treatment adherence in polymedicated patients.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

Analysis and Deployment of Applications Acceleration Environment for Xilinx Hardware-Accelerated Platforms.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

The influence of virtualization on real-time systems' interrupts in embedded SoC platforms.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021
Fast and efficient address search in System-on-a-Programmable-Chip using binary trees.
Comput. Electr. Eng., 2021

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems.
IEEE Access, 2021

Evaluating the OpenAMP framework in real-time embedded SoC platforms.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

Analysing the interference of Xen hypervisor in the network speed.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

Electronic control board for student Rocket.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Smart Sensor: SoC Architecture for the Industrial Internet of Things.
IEEE Internet Things J., 2019

Fast and efficient FPGA prototype system for embedded control algorithms in electric traction.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
SEU emulation in industrial SoCs combining microprocessor and FPGA.
Reliab. Eng. Syst. Saf., 2018

System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems.
IEEE Trans. Smart Grid, 2017

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs.
Microelectron. Reliab., 2017

A novel BRAM content accessing and processing method based on FPGA configuration bitstream.
Microprocess. Microsystems, 2017

Cyber-Physical Production System Gateway Based on a Programmable SoC Platform.
IEEE Access, 2017

2016
Intelligent gateway for Industry 4.0-compliant production.
Proceedings of the IECON 2016, 2016

2015
PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding.
IEEE Trans. Smart Grid, 2015

2014
FTL-CFree: A Fuzzy Real-Time Language for Runtime Verification.
IEEE Trans. Ind. Informatics, 2014

Cost-effective redundancy for ethernet train communications using HSR.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Securing IEEE 1588 messages with message authentication codes based on the KECCAK cryptographic algorithm implemented in FPGAs.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Fast and accurate SEU-tolerance characterization method for Zynq SoCs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
IEEE 1588 Transparent Clock architecture for FPGA-based network devices.
Proceedings of the 22nd IEEE International Symposium on Industrial Electronics, 2013

System-on-Chip implementation of Reliable Ethernet Networks nodes.
Proceedings of the IECON 2013, 2013

Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3).
Proceedings of the IECON 2013, 2013

PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation.
Proceedings of the IECON 2013, 2013

Memory requirements analysis for PRP and HSR hardware implementations on FPGAs.
Proceedings of the IECON 2013, 2013

SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

High availability automation networks: PRP and HSR ring implementations.
Proceedings of the 21st IEEE International Symposium on Industrial Electronics, 2012

2011
I2CSec: A secure serial Chip-to-Chip communication protocol.
J. Syst. Archit., 2011

NoCmodel: An extensible framework for Network-on-Chips modeling.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2010
Neuro semantic thresholding using OCR software for high precision OCR applications.
Image Vis. Comput., 2010

An Autonomous Fault Tolerant System for CAN Communications.
Proceedings of the Trends in Applied Intelligent Systems, 2010

2009
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus.
Proceedings of the 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 2009

AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Configurable-System-on-Programmable-Chip for Power Electronics Control Applications.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes.
Proceedings of the Autonomic and Trusted Computing, 5th International Conference, 2008

2007
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs.
J. Syst. Archit., 2007

Hardware architecture for a general regression neural network coprocessor.
Neurocomputing, 2007

GPS-less location algorithm for wireless sensor networks.
Comput. Commun., 2007

2006
SOM Segmentation of gray scale images for optical recognition.
Pattern Recognit. Lett., 2006

Node Synchronization in Wireless Sensor Networks.
Proceedings of the Second International Conference on Wireless and Mobile Communications (ICWMC'06), 2006

2005
Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications.
Microprocess. Microsystems, 2005

Multiprocessor SoPC-Core for FAT volume computation.
Microprocess. Microsystems, 2005

Hardware implementation of optical flow constraint equation using FPGAs.
Comput. Vis. Image Underst., 2005

2004
Malguki: an RSSI based ad hoc location algorithm.
Microprocess. Microsystems, 2004

Basque: A Case Study in Generalizing LaTeX Language Support.
Proceedings of the TeX, 2004

Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development.
Proceedings of the International Conference on Modeling, 2004

Doppler Location Algorithm for Wireless Sensor Networks.
Proceedings of the International Conference on Wireless Networks, 2004

High Throughput Serpent Encryption Implementation.
Proceedings of the Field Programmable Logic and Application, 2004

A Self-Reconfiguration Framework for Multiprocessor CSoPCs.
Proceedings of the Field Programmable Logic and Application, 2004

An Electronic Secure Voting System Based on Automatic Paper Ballot Reading.
Proceedings of the Progress in Pattern Recognition, 2004

2003
Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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