Paul Pop

Orcid: 0000-0001-9981-1775

According to our database1, Paul Pop authored at least 137 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Configuration optimization for heterogeneous time-sensitive networks.
Real Time Syst., December, 2023

SRv6-based Time-Sensitive Networks (TSN) with low-overhead rerouting.
Int. J. Netw. Manag., 2023

Mapping and Integration of Event- and Time-triggered Real-time Tasks on Partitioned Multi-core Systems.
Proceedings of the 28th IEEE International Conference on Emerging Technologies and Factory Automation, 2023

The FORA European Training Network on Fog Computing for Robotics and Industrial Automation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Special Session: Digital Technologies for Sustainability - Research Challenges and Opportunities.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2022
Quantitative Performance Comparison of Various Traffic Shapers in Time-Sensitive Networking.
IEEE Trans. Netw. Serv. Manag., 2022

Extensibility-aware Fog Computing Platform configuration for mixed-criticality applications.
J. Syst. Archit., 2022

Dependability-aware routing and scheduling for Time-Sensitive Networking.
IET Cyper-Phys. Syst.: Theory & Appl., 2022

Configuration and Evaluation of Multi-CQF Shapers in IEEE 802.1 Time-Sensitive Networking (TSN).
IEEE Access, 2022

Real-Time Traffic Guarantees in Heterogeneous Time-sensitive Networks.
Proceedings of the RTNS 2022: The 30th International Conference on Real-Time Networks and Systems, Paris, France, June 7, 2022

Latency-Aware Function Placement, Routing, and Scheduling in TSN-based Industrial Networks.
Proceedings of the IEEE International Conference on Communications, 2022

Active Connectivity Fundamentals for TSCH Networks of Mobile Robots.
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022

2021
Latency Analysis of Multiple Classes of AVB Traffic in TSN With Standard Credit Behavior Using Network Calculus.
IEEE Trans. Ind. Electron., 2021

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

The FORA Fog Computing Platform for Industrial IoT.
Inf. Syst., 2021

Improving Latency Analysis for Flexible Window-Based GCL Scheduling in TSN Networks by Integration of Consecutive Nodes Offsets.
IEEE Internet Things J., 2021

Configuring ADAS Platforms for Automotive Applications Using Metaheuristics.
Frontiers Robotics AI, 2021

TSCH Evaluation under heterogeneous Mobile Scenarios.
CoRR, 2021

Real-Time Guarantees for Critical Traffic in IEEE 802.1Qbv TSN Networks with Unscheduled and Unsynchronized End-Systems.
CoRR, 2021

Communication Scheduling for Control Performance in TSN-Based Fog Computing Platforms.
IEEE Access, 2021

Failure Handling for Time-Sensitive Networks using SDN and Source Routing.
Proceedings of the 7th IEEE International Conference on Network Softwarization, 2021

Scheduling Real-Time Applications on Edge Computing Platforms with Remote Attestation for Security.
Proceedings of the 6th IEEE/ACM Symposium on Edge Computing, 2021

2020
Traffic-type Assignment for TSN-based Mixed-criticality Cyber-physical Systems.
ACM Trans. Cyber Phys. Syst., 2020

Distributed control plane for safe cooperative vehicular cyber physical systems.
IET Cyper-Phys. Syst.: Theory & Appl., 2020

Performance Optimization of Control Applications on Fog Computing Platforms Using Scheduling and Isolation.
IEEE Access, 2020

Window-Based Schedule Synthesis for Industrial IEEE 802.1Qbv TSN Networks.
Proceedings of the 16th IEEE International Conference on Factory Communication Systems, 2020

Work-In-Progress: Safe and Secure Configuration Synthesis for TSN using Constraint Programming.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

Efficient Hosting of Robust IoT Applications on Edge Computing Platform.
Proceedings of the 4th IEEE International Conference on Fog and Edge Computing, 2020

Quality-Of-Control-Aware Scheduling of Communication in TSN-Based Fog Computing Platforms Using Constraint Programming.
Proceedings of the 2nd Workshop on Fog Computing and the IoT, 2020

Mapping and Scheduling Automotive Applications on ADAS Platforms using Metaheuristics.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

Fogification of electric drives: An industrial use case.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

Towards Extensibility-Aware Scheduling of Industrial Applications on Fog Nodes.
Proceedings of the 2020 IEEE International Conference on Edge Computing, 2020

2019
Design-for-Testability of On-Chip Control in mVLSI Biochips.
IEEE Des. Test, 2019

Cooperative Resource Allocation and Scheduling for 5G eV2X Services.
IEEE Access, 2019

Ultra Reliable Distributed Control for Cooperative Vehicular Cyber Physical Systems.
Proceedings of the 2019 IEEE International Systems Conference, 2019

Towards quality-of-control-aware scheduling of industrial applications on fog computing platforms.
Proceedings of the Workshop on Fog Computing and the IoT, 2019

Dependable Wireless Industrial IoT Networks: Recent Advances and Open Challenges.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Enabling Fog Computing for Industrial Automation Through Time-Sensitive Networking (TSN).
IEEE Commun. Stand. Mag., 2018

Worst-Case Latency Analysis for IEEE 802.1Qbv Time Sensitive Networks Using Network Calculus.
IEEE Access, 2018

AVB-Aware Routing and Scheduling of Time-Triggered Traffic for TSN.
IEEE Access, 2018

Scheduling in time sensitive networks (TSN) for mixed-criticality industrial applications.
Proceedings of the 14th IEEE International Workshop on Factory Communication Systems, 2018

Timing Analysis of AVB Traffic in TSN Networks Using Network Calculus.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2018

Enhanced 5G V2X services using sidelink device-to-device communications.
Proceedings of the 17th Annual Mediterranean Ad Hoc Networking Workshop, 2018

2017
Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Timing analysis of rate-constrained traffic in TTEthernet using network calculus.
Real Time Syst., 2017

Safe cooperating cyber-physical systems using wireless communication: The SafeCOP approach.
Microprocess. Microsystems, 2017

Design optimization for security- and safety-critical distributed real-time applications.
Microprocess. Microsystems, 2017

Fault-tolerant topology and routing synthesis for IEEE time-sensitive networking.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

Runtime reconfiguration of time-sensitive networking (TSN) schedules for Fog Computing.
Proceedings of the IEEE Fog World Congress, 2017

Volume management for fault-tolerant continuous-flow microfluidics.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Synthesis of on-chip control circuits for mVLSI biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
Proceedings of the 54th Annual Design Automation Conference, 2017

Towards industry strength mapping of AUTOSAR automotive functionality on multicore architectures: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Routing optimization of AVB streams in TSN networks.
SIGBED Rev., 2016

Traffic class assignment for mixed-criticality frames in TTEthernet.
SIGBED Rev., 2016

Design optimisation of cyber-physical distributed systems using IEEE time-sensitive networks.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

The SafeCOP ECSEL Project: Safe Cooperating Cyber-Physical Systems Using Wireless Communication.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Architecture synthesis for cost-constrained fault-tolerant flow-based biochips.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Design Optimization of Mixed-Criticality Real-Time Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2015

Design optimization of TTEthernet-based distributed real-time systems.
Real Time Syst., 2015

System-level synthesis of multi-ASIP platforms using an uncertainty model.
Integr., 2015

Synthesis of biochemical applications on digital microfluidic biochips with operation execution time variability.
Integr., 2015

Continuous-Flow Biochips: Technology, Physical-Design Methods, and Testing.
IEEE Des. Test, 2015

Redundancy optimization for error recovery in digital microfluidic biochips.
Des. Autom. Embed. Syst., 2015

Timing Analysis of Rate Constrained Traffic for the TTEthernet Communication Protocol.
Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015

Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Optimization of Partitioned Architectures to Support Soft Real-Time Applications.
Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

Online synthesis for operation execution time variability on digital microfluidic biochips.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Optimization of TTEthernet networks to support best-effort traffic.
Proceedings of the 2014 IEEE Emerging Technology and Factory Automation, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocess. Microsystems, 2013

Module-Based Synthesis of Digital Microfluidic Biochips with Droplet-Aware Operation Execution.
ACM J. Emerg. Technol. Comput. Syst., 2013

Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Multi-ASIP platform synthesis for real-time applications.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Multi-ASIP platform synthesis for Event-Triggered applications with cost/performance trade-offs.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Hierarchical DSE for multi-ASIP platforms.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Control synthesis for the flow-based microfluidic large-scale integration biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs.
ACM Trans. Embed. Comput. Syst., 2012

Routing-based synthesis of digital microfluidic biochips.
Des. Autom. Embed. Syst., 2012

SAFCM: A Security-Aware Feedback Control Mechanism for Distributed Real-Time Embedded Systems.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Timing analysis of mixed-criticality hard real-time applications implemented on distributed partitioned architectures.
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Robust and flexible mapping for real-time distributed applications during the early design phases.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synthesis of communication schedules for TTEthernet-based mixed-criticality systems.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Architectural synthesis of flow-based microfluidic large-scale integration biochips.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Design Optimization of Mixed-Criticality Real-Time Applications on Cost-Constrained Partitioned Architectures.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

Task Mapping and Partition Allocation for Mixed-Criticality Real-Time Systems.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

Optimization of Time-Partitions for Mixed-Criticality Real-Time Distributed Embedded Systems.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Digital microfluidic biochips: recent research and emerging challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

System-level modeling and synthesis of flow-based microfluidic biochips.
Proceedings of the 14th International Conference on Compilers, 2011

Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Application-aware optimization of redundant resources for the reconfigurable self-healing eDNA hardware architecture.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Tabu search-based synthesis of digital microfluidic biochips with dynamically reconfigurable non-rectangular devices.
Des. Autom. Embed. Syst., 2010

Task Mapping and Bandwidth Reservation for Mixed Hard/Soft Fault-Tolerant Embedded Systems.
Proceedings of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, 2010

2009
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Task migration for fault-tolerance in mixed-criticality embedded systems.
SIGBED Rev., 2009

Analysis and optimization of fault-tolerant embedded systems with hardened processors.
Proceedings of the Design, Automation and Test in Europe, 2009

Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Timing analysis of the FlexRay communication protocol.
Real Time Syst., 2008

Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems.
Int. J. Parallel Program., 2008

Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Synthesis of Fault-Tolerant Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A constraint logic programming framework for the synthesis of fault-tolerant schedules for distributed embedded systems.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

Bus access optimisation for FlexRay-based distributed embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Analysis and optimization of distributed real-time embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2006

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Schedulability-driven frame packing for multicluster distributed embedded systems.
ACM Trans. Embed. Comput. Syst., 2005

Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems.
Proceedings of the 2005 Design, 2005

Embedded Systems Design: Optimization Challenges.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2005

2004
Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems.
Real Time Syst., 2004

Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems.
Proceedings of the 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June, 2004

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application.
Proceedings of the 2004 Design, 2004

Analysis and synthesis of distributed real-time embedded systems.
Springer, ISBN: 978-1-4020-2872-4, 2004

2003
Schedulability-driven frame packing for multi-cluster distributed embedded systems.
Proceedings of the 2003 Conference on Languages, 2003

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems.
Proceedings of the 2003 Design, 2003

2001
An Approach to Incremental Design of Distributed Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001

Minimizing system modification in an incremental design approach.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Scheduling with bus access optimization for distributed embedded systems.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Schedulability analysis for systems with data and control dependencies.
Proceedings of the 12th Euromicro Conference on Real-Time Systems (ECRTS 2000), 2000

Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis.
Proceedings of the 2000 Design, 2000

Performance estimation for embedded systems with data and control dependencies.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
An Improved Scheduling Technique for Time-Triggered Embedded Systems.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Scheduling with optimized communication for time-triggered embedded systems.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.
Proceedings of the 1998 Design, 1998


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