Krzysztof Kuchcinski

Microprocess. Microsystems, 2019

2016

Code generation for a SIMD architecture with custom memory organisation.

[BibT_eX]

[DOI]

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015

A Comparative Study of Scheduling Techniques for Multimedia Applications on SIMD Pipelines.

[BibT_eX]

[DOI]

CoRR, 2015

Programming support for reconfigurable custom vector architectures.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Programming Models and Applications for Multicores and Manycores, 2015

Application-set driven exploration for custom processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Instruction selection and scheduling for DSP kernels.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip.

[BibT_eX]

[DOI]

Usman Mazhar Mirza

Comput. Electr. Eng., 2014

Lessons from ten years of the international master's program in System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013

Design space exploration for streaming applications on multiprocessors with guaranteed service NoC.

[BibT_eX]

[DOI]

Usman Mazhar Mirza

Proceedings of the Network on Chip Architectures, 2013

Instruction Selection and Scheduling for DSP Kernels on Custom Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2012

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2012

Partitioning and mapping dynamic dataflow programs.

[BibT_eX]

[DOI]

Jörn W. Janneck

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

Exploring Software Product Management decision problems with constraint solving - opportunities for prioritization and release planning.

[BibT_eX]

[DOI]

Björn Regnell

Proceedings of the 5th International Workshop on Software Product Management, 2011

Distributed Constraint Programming with Agents.

[BibT_eX]

[DOI]

Proceedings of the Adaptive and Intelligent Systems - Second International Conference, 2011

2010

Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Combined scheduling and instruction selection for processors with reconfigurable cell fabric.

[BibT_eX]

[DOI]

Antoine Floch

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel.

[BibT_eX]

[DOI]

Erwan Raffin

ACM Trans. Design Autom. Electr. Syst., 2009

Constraint-Driven Identification of Application Specific Instructions in the <i>DURASE</i> System.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2009

Parallel Consistency in Constraint Programming.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Design space exploration for optimal memory mapping of data and instructions in multimedia applications to Scratch-Pad Memories.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions.

[BibT_eX]

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Architecture-Driven Synthesis of Reconfigurable Cells.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

State-copying and Recomputation in Parallel Constraint Programming with Global Constraints.

[BibT_eX]

[DOI]

Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Automatic Selection of Application-Specific Reconfigurable Processor Extensions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Load-balancing methods for parallel and distributed constraint solving.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September, 2008

2007

A CP-LP approach to network management in OSPF routing.

[BibT_eX]

[DOI]

Mats Petter Pettersson

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

A New Necessary Condition for Shortest Path Routing.

[BibT_eX]

[DOI]

Mats Petter Pettersson

Proceedings of the Network Control and Optimization, 2007

Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware.

[BibT_eX]

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Graph Matching Constraints for Synthesis with Complex Components.

[BibT_eX]

[DOI]

Ana Fuentes Martinez

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Performance Improvement for H.264 Video Encoding using ILP Embedded Processor.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Automatic generation of application-specific systems based on a micro-programmed Java core.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Implementation aspects of a novel speech packet loss concealment method.

[BibT_eX]

[DOI]

Henrik Svensson

Viktor Öwall

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Constraints Programming Approach for Fabric Cell Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Java to Hardware Compilation for non Data Flow Applications.

[BibT_eX]

[DOI]

Per Andersson

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

A constraints programming approach to communication scheduling on SoPC architectures.

[BibT_eX]

[DOI]

Maya B. Gokhale

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Data assignment and access scheduling exploration for multi-layer memory architectures.

[BibT_eX]

[DOI]

Francky Catthoor

Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths.

[BibT_eX]

Per Andersson

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Time-Energy Design Space Exploration for Multi-Layer Memory Architectures.

[BibT_eX]

[DOI]

Francky Catthoor

Proceedings of the 2004 Design, 2004

2003

Constraints-driven scheduling and resource assignment.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Partial task assignment of task graphs under heterogeneous resource constraints.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Integrating a Computational Model and a Run Time System for Image Processing on a UAV.

[BibT_eX]

[DOI]

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

Constraints-driven design space exploration for distributed embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2001

Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

A constructive algorithm for memory-aware task assignment and scheduling.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

LEneS: task scheduling for low-energy systems using variable supply voltage processors.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Digital Systems Design Using Constraint Logic Programming.

[BibT_eX]

Proceedings of the Second International Conference on the Practical Application of Constraint Technologies and Logic Programming, 2000

Task Assignment and Scheduling under Memory Constraints.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Performance Oriented Partitioning for Time-Multiplexed FPGA's.

[BibT_eX]

[DOI]

Per Andersson

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

The WITAS Unmanned Aerial Vehicle Project.

[BibT_eX]

Proceedings of the ECAI 2000, 2000

1999

Design Space Exploration in System Level Synthesis under Memory Constraints.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Synthesis of Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

An Approach to High-Level Synthesis Using Constraint Logic Programming.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Operation Binding and Scheduling for Low Power Using Constraint Logic Programming.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Design of hardware and software systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 1997

Post-synthesis back-annotation of timing information in behavioral VHDL.

[BibT_eX]

[DOI]

J. Syst. Archit., 1997

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1997

Embedded System Synthesis by Timing Constraints Solving.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on System Synthesis, 1997

A controller testability analysis and enhancement technique.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Synthesis of systems specified as interacting VHDL processes.

[BibT_eX]

[DOI]

Petru Eles

Integr., 1996

Hardware/Software Partitioning with Iterative Improvement Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on System Synthesis, 1996

Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 22rd EUROMICRO Conference '96, 1996

Hardware/software partitioning of VHDL system specifications.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

An Efficient and Economic Partitioning Approach for Testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Timing constraint specification and synthesis in behavioral VHDL.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Automated transformation of algorithms into register-transfer level implementations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Testability analysis and improvement from VHDL behavioral specifications.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Synthesis of VHDL concurrent processes.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

System level modelling and analysis of complex digital systems.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

Automatic Diagnosis of VLSI Digital Circuits Using Algorithmic Debugging.

[BibT_eX]

[DOI]

Wlodzimierz Drabent

Jan Maluszynski

Proceedings of the Automated and Algorithmic Debugging, First International Workshop, 1993

1992

An approach to testability analysis and improvement for VLSI systems.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1992

Compiling VHDL into a high-level synthesis design representation.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

Testability measure with reconvergent fanout analysis and its applications.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1991

1990

Testability analysis in a VLSI high-level synthesis system.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1990

1988

Parallelism extraction from sequential programs for VLSI applications.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

Path analysis of distributed programs.

[BibT_eX]

[DOI]

Bogdan Wiszniewski

Proceedings of the Sixteenth ACM Annual Conference on Computer Science, 1988

1987

Microprogramming implementation of timed Petri nets.

[BibT_eX]

[DOI]