Alex Shye

According to our database1, Alex Shye authored at least 11 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Characterizing and modeling user activity on smartphones: summary.
Proceedings of the SIGMETRICS 2010, 2010

2009
PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures.
IEEE Trans. Dependable Secur. Comput., 2009

Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008
Power to the people: Leveraging human physiological traits to control microprocessor frequency.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Shadow Profiling: Hiding Instrumentation Costs with Parallelism.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2005
Dynamic run-time architecture techniques for enabling continuous optimization.
Proceedings of the Second Conference on Computing Frontiers, 2005

Code coverage testing using hardware performance monitoring support.
Proceedings of the Sixth International Workshop on Automated Debugging, 2005

Analysis of path profiling information generated with performance monitoring hardware.
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005


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