Alex Settle

According to our database1, Alex Settle authored at least 7 papers between 2003 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2006
A dynamically reconfigurable cache for multithreaded processors.
J. Embedded Computing, 2006

2005
Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors.
J. Instruction-Level Parallelism, 2005

Dynamic run-time architecture techniques for enabling continuous optimization.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
PIN: a binary instrumentation tool for computer architecture research and education.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Architectural Support for Enhanced SMT Job Scheduling.
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003
Optimization for the Intel® Itanium ®Architectur Register Stack.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

Compiler-Directed Resource Management for Active Code Regions.
Proceedings of the 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 2003


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