Daniel A. Connors
According to our database1, Daniel A. Connors authored at least 50 papers between 1994 and 2015.
Legend:Book In proceedings Article PhD thesis Other
PyCompArch: python-based modules for exploring computer architecture concepts.
Proceedings of the Workshop on Computer Architecture Education, 2015
Data-driven techniques to overcome workload disparity.
Proceedings of the Fourth Workshop on Irregular Applications, 2014
Exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systems.
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013
Natural Load Indices (NLI) for scientific simulation.
The Journal of Supercomputing, 2012
A Framework for Automated Performance Tuning and Code Verification on GPU Computing Platforms.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Modeling Ion Channel Kinetics with HPC.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures.
IEEE Trans. Dependable Sec. Comput., 2009
Hardware-compiler co-design for adjustable data power savings.
Microprocess. Microsystems, 2009
An efficient lock-aware transactional memory implementation.
Proceedings of the 4th workshop on the Implementation, 2009
Optimizing consistency checking for memory-intensive transactions.
Proceedings of the Twenty-Seventh Annual ACM Symposium on Principles of Distributed Computing, 2008
Teaching Fault Tolerant FPGA Design for Aerospace Applications.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Phase-Guided Small-Sample Simulation.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007
Identifying potential parallelism via loop-centric profiling.
Proceedings of the 4th Conference on Computing Frontiers, 2007
An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance.
IEEE Micro, 2006
A dynamically reconfigurable cache for multithreaded processors.
J. Embedded Computing, 2006
Improved stride prefetching using extrinsic stream characteristics.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
Chip multi-processor scalability for single-threaded applications.
SIGARCH Computer Architecture News, 2005
Persistence in dynamic code transformation systems.
SIGARCH Computer Architecture News, 2005
Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors.
J. Instruction-Level Parallelism, 2005
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005
Statistical Simulation of Multithreaded Architectures.
Proceedings of the 13th International Symposium on Modeling, 2005
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Dynamic run-time architecture techniques for enabling continuous optimization.
Proceedings of the Second Conference on Computing Frontiers, 2005
Code coverage testing using hardware performance monitoring support.
Proceedings of the Sixth International Workshop on Automated Debugging, 2005
Analysis of path profiling information generated with performance monitoring hardware.
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005
PIN: a binary instrumentation tool for computer architecture research and education.
Proceedings of the 2004 workshop on Computer architecture education, 2004
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
A VFSA Scheduler for Radiative Transfer Data in Climate Models.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004
Architectural Support for Enhanced SMT Job Scheduling.
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004
The analysis and design of architecture systems for speech recognition on modern handheld-computing devices.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Optimization for the Intel® Itanium ®Architectur Register Stack.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003
Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
Compiler-Directed Resource Management for Active Code Regions.
Proceedings of the 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 2003
Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000
Proceedings of the VLSI Handbook., 1999
Run-Time Cache Bypassing.
IEEE Trans. Computers, 1999
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
The Program Decision Logic Approach to Predicated Execution.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999
An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
Compiler-Directed Early Load-Address Generation.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998
Run-Time Adaptive Cache Management.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997
Scheduling semiconductor lines using a fluid network model.
IEEE Trans. Robotics and Automation, 1994