Tipp Moseley

Orcid: 0009-0003-5042-440X

According to our database1, Tipp Moseley authored at least 23 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2021
Beyond malloc efficiency to fleet efficiency: a hugepage-aware memory allocator.
Proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation, 2021

Break dancing: low overhead, architecture neutral software branch tracing.
Proceedings of the LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, 2021

2020
AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers.
IEEE Micro, 2020

2016
Profiling a Warehouse-Scale Computer.
IEEE Micro, 2016

AutoFDO: automatic feedback-directed optimization for warehouse-scale applications.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

2013
Instant profiling: Instrumentation sampling for profiling datacenter applications.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
Measuring interference between live datacenter applications.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

2011
Hardware Performance Monitoring for the Rest of Us: A Position and Survey.
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

2010
Google-Wide Profiling: A Continuous Profiling Infrastructure for Data Centers.
IEEE Micro, 2010

2009
PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures.
IEEE Trans. Dependable Secur. Comput., 2009

A Balanced Approach to Application Performance Tuning.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

OptiScope: Performance Accountability for Optimizing Compilers.
Proceedings of the CGO 2009, 2009

Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison.
Proceedings of the PACT 2009, 2009

2008
FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

2007
Seekable Compressed Traces.
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Shadow Profiling: Hiding Instrumentation Costs with Parallelism.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Identifying potential parallelism via loop-centric profiling.
Proceedings of the 4th Conference on Computing Frontiers, 2007

FastForward for Efficient Pipeline Parallelism.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2005
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Dynamic run-time architecture techniques for enabling continuous optimization.
Proceedings of the Second Conference on Computing Frontiers, 2005

Analysis of path profiling information generated with performance monitoring hardware.
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005


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