Alexandre Guerre

According to our database1, Alexandre Guerre authored at least 15 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Specific Read-Only Data Management for Memory System Optimization.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

HARS: A hardware-assisted runtime software for embedded many-core architectures.
ACM Trans. Embedded Comput. Syst., 2014

Specific read only data management for memory hierarchy optimization.
SIGBED Review, 2014

Specific Read Only Data Management for Memory Hierarchy Optimization.
Proceedings of the Embed With Linux 2014 Workshop, Lisboa, Portugal, November 13-14, 2014., 2014

Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Early design stage thermal evaluation and mitigation: The locomotiv architectural case.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A unified methodology for a fast benchmarking of parallel architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

PACHA: Low Cost Bare Metal Development for Shared Memory Manycore Accelerators.
Proceedings of the International Conference on Computational Science, 2013

ARTM: a lightweight fork-join framework for many-core embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2013

SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Hierarchical Network-on-Chip for Embedded Many-Core Architectures.
Proceedings of the NOCS 2010, 2010

SESAM: An MPSoC Simulation Environment for Dynamic Application Processing.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009