Caaliph Andriamisaina

According to our database, Caaliph Andriamisaina authored at least 13 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing.

Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton

IEEE J. Solid State Circuits, 2019

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design.

Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux

Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

2018

A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing.

Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2014

HARS: A hardware-assisted runtime software for embedded many-core architectures.

Yves Lhuillier, Maroun Ojail, Alexandre Guerre, Jean-Marc Philippe, Karim Ben Chehida, Farhat Thabet, Caaliph Andriamisaina, Chafic Jaber, Raphaël David

ACM Trans. Embed. Comput. Syst., 2014

2013

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture.

Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David

Proceedings of the Design, Automation and Test in Europe, 2013

2010

High-Level Synthesis for Designing Multimode Architectures.

Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.

Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina

Tech. Sci. Informatiques, 2008

2007

A design flow dedicated to multi-mode architectures for DSP applications.

Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Synthesis of Multimode digital signal processing systems.

Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques.

Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou

Tech. Sci. Informatiques, 2006

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems.

Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.

Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005

Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.

Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005