Caaliph Andriamisaina

According to our database1, Caaliph Andriamisaina authored at least 12 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing.
J. Solid-State Circuits, 2019

2018
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2014
HARS: A hardware-assisted runtime software for embedded many-core architectures.
ACM Trans. Embedded Comput. Syst., 2014

2013
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture.
Proceedings of the Design, Automation and Test in Europe, 2013

2010
High-Level Synthesis for Designing Multimode Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

2008
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.
Technique et Science Informatiques, 2008

2007
A design flow dedicated to multi-mode architectures for DSP applications.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Synthesis of Multimode digital signal processing systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques.
Technique et Science Informatiques, 2006

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005


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