Ronan Keryell

Orcid: 0000-0001-8781-985X

According to our database1, Ronan Keryell authored at least 25 papers between 1991 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Tutorial: SYCL Techniques and Best Practices.
Proceedings of the 2023 International Workshop on OpenCL, 2023

2022
Tutorial: Application Development with SYCL.
Proceedings of the IWOCL'22: International Workshop on OpenCL, Bristol, United Kingdom, May 10, 2022

Using interoperability mode in SYCL 2020.
Proceedings of the IWOCL'22: International Workshop on OpenCL, Bristol, United Kingdom, May 10, 2022

A single-source C++20 HLS flow for function evaluation on FPGA and beyond.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

2021
A Hands-On Introduction To SYCL.
Proceedings of the IWOCL'21: International Workshop on OpenCL, Munich Germany, April, 2021, 2021

2018
Early experiments using SYCL single-source modern C++ on Xilinx FPGA: Extended Abstract of Technical Presentation.
Proceedings of the International Workshop on OpenCL, 2018

2017
SYCL C++ and OpenCL interoperability experimentation with triSYCL.
Proceedings of the 5th International Workshop on OpenCL, 2017

2016
Optimizing OpenCL applications on Xilinx FPGA.
Proceedings of the 4th International Workshop on OpenCL, 2016

2015
Khronos SYCL for OpenCL: a tutorial.
Proceedings of the 3rd International Workshop on OpenCL, 2015

2013
Compilation pour cibles hétérogènes. Le cas Terapix.
Tech. Sci. Informatiques, 2013

2012
Polyèdres et compilation.
Tech. Sci. Informatiques, 2012

Compilation et optimisation statique des communications hôte-accélérateur.
Tech. Sci. Informatiques, 2012

SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

2011
Static Compilation Analysis for Host-Accelerator Communication Optimization.
Proceedings of the Languages and Compilers for Parallel Computing, 2011

Building Retargetable and Efficient Compilers for Multimedia Instruction Sets.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2008
Improving virus protection with an efficient secure architecture with memory encryption, integrity and information leakage protection.
J. Comput. Virol., 2008

CryptoPage. Une architecture efficace combinant chiffrement, intégrité mémoire et protection contre les fuites d'informations permettant du calcul distribué sr.
Tech. Sci. Informatiques, 2008

Building Secure Resources to Ensure Safe Computations in Distributed and Potentially Corrupted Environments.
Proceedings of the Euro-Par 2008 Workshops, 2008

2006
CryptoPage: An Efficient Secure Architecture with Memory Encryption, Integrity and Information Leakage Protection.
Proceedings of the 22nd Annual Computer Security Applications Conference (ACSAC 2006), 2006

2005
CryptoPage : Support matériel pour cryptoprocessus.
Tech. Sci. Informatiques, 2005

Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.
Proceedings of the Computer Systems: Architectures, 2004

1997
A Linear Algebra Framework for Static High Performance Fortran Code Distribution.
Sci. Program., 1997

1993
Activity Counter: New Optimization for the Dynamic Scheduling of SIMD Control Flow.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1991
POMP or How to Design a Massively Parallel Machine with Small Developments.
Proceedings of the PARLE '91: Parallel Architectures and Languages Europe, 1991


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