Alireza Namazi

Orcid: 0000-0001-8620-292X

According to our database1, Alireza Namazi authored at least 14 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2019
CMV: Clustered Majority Voting Reliability-Aware Task Scheduling for Multicore Real-Time Systems.
IEEE Trans. Reliab., 2019

SORT: Semi Online Reliable Task Mapping for Embedded Multi-Core Systems.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2019

2018
A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC Architectures.
ACM Trans. Embed. Comput. Syst., 2018

LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

2017
LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications.
Proceedings of the Euromicro Conference on Digital System Design, 2017

PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Clustering Effects on the Design of Opto-Electrical Network-on-Chip.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

LPVM: Low-Power Variation-Mitigant Adder Architecture Using Carry Expedition.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

2011
Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors.
Microelectron. Reliab., 2011

2009
A low-cost fault-tolerant technique for Carry Look-Ahead adder.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.
Proceedings of the The Forth International Conference on Availability, 2009

2004
Extended Floor Field CA Model for Evacuation Dynamics.
IEICE Trans. Inf. Syst., 2004


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