Anandkumar Mahadevan Pillai

According to our database, Anandkumar Mahadevan Pillai authored at least 3 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

29.2 A 0.021µm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery.

Xiaofei Wang, Yusung Kim, Gwanghyeon Baek, Kunal Girish Bannore, Kaushal Dave, Arash Joushaghani, Narae Kang, Minwoo Ko, Anandkumar Mahadevan Pillai, Hema Chandra Prakash Movva, Gyusung Park, Muktadir Rahman, Seenivasan Subramaniam, Vinay Vashishtha, Teng Yang, Zheng Guo, Eric A. Karl

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.

Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology.

Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl

IEEE J. Solid State Circuits, 2023