Kunal Bannore

According to our database, Kunal Bannore authored at least 3 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

0.021-μm² High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery.

Xiaofei Wang, Gwanghyeon Baek, Kunal Girish Bannore, Kaushal Dave, Arash Joushaghani, Minwoo Ko, Anandkumar Mahadevan Pillai, Hema Chandra Prakash Movva, Gyusung Park, Seenivasan Subramaniam, Teng Yang, Zheng Guo, Fatih Hamzaoglu, Eric A. Karl

IEEE J. Solid State Circuits, January, 2026

2025

29.2 A 0.021µm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery.

Xiaofei Wang, Yusung Kim, Gwanghyeon Baek, Kunal Girish Bannore, Kaushal Dave, Arash Joushaghani, Narae Kang, Minwoo Ko, Anandkumar Mahadevan Pillai, Hema Chandra Prakash Movva, Gyusung Park, Muktadir Rahman, Seenivasan Subramaniam, Vinay Vashishtha, Teng Yang, Zheng Guo, Eric A. Karl

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.

Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl

Proceedings of the IEEE International Solid-State Circuits Conference, 2024