Daeyeon Kim
Orcid: 0000-0002-5879-8313
According to our database1,
Daeyeon Kim
authored at least 48 papers
between 2009 and 2024.
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Bibliography
2024
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
Parallelized Particle Filter With Efficient Pipelining on FPGA for Real-Time Ballistic Target Tracking.
IEEE Access, 2023
IEEE Access, 2023
Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization.
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
2019
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications.
IEEE J. Solid State Circuits, 2019
DMS: Dynamic Model Scaling for Quality-Aware Deep Learning Inference in Mobile and Embedded Devices.
IEEE Access, 2019
2018
A 23.6Mb/mm<sup>2</sup> SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Poster Abstract: DeepRT: A Predictable Deep Learning Inference Framework for IoT Devices.
Proceedings of the 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2016
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.
IEEE J. Solid State Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
IEEE Wirel. Commun. Lett., 2013
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs).
IEEE Trans. Very Large Scale Integr. Syst., 2013
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.
IEEE J. Solid State Circuits, 2013
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
IEEE J. Solid State Circuits, 2013
A resource allocation algorithm for OFDM-based cellular system serving unicast and multicast services.
EURASIP J. Wirel. Commun. Netw., 2013
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013
2012
EURASIP J. Wirel. Commun. Netw., 2012
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
OFDMA resource allocation for multicasting videos to users with diverse screen sizes.
Proceedings of the IEEE International Conference on Communication Systems, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the European Workshop on Visual Information Processing, 2011
2010
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the Sixth Advanced International Conference on Telecommunications, 2010
Resource Allocation Method for OFDM System to Transmit SVC over Frequency Selective Channel.
Proceedings of the Sixth Advanced International Conference on Telecommunications, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009