Vinay Vashishtha

According to our database, Vinay Vashishtha authored at least 11 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

ASAP5: A predictive PDK for the 5 nm node.

Vinay Vashishtha, Lawrence T. Clark

Microelectron. J., 2022

2021

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node.

Vinay Vashishtha, Lawrence T. Clark

Microelectron. J., 2021

2017

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.

Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit.

Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Robust 7-nm SRAM design on a predictive PDK.

Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper.

Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design with sub-10 nm FinFET technologies.

Lawrence T. Clark, Vinay Vashishtha

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

ASAP7: A 7-nm finFET predictive process design kit.

Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric

Microelectron. J., 2016

2015

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation.

Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Delay and power tradeoffs for static and dynamic register files.

Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A soft-error hardened process portable embedded microprocessor.

Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015