Nicholas C. Rumin

According to our database, Nicholas C. Rumin authored at least 20 papers between 1984 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2005

Explicit delay metric for interconnect optimization.

Min Ma, Mourad Oulmane, Nicholas C. Rumin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2001

Delay and current estimation in a CMOS inverter with an RC load.

Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

1999

An analytical current, delay, and power model for the submicron CMOS inverter.

Anas A. Hamoui, Nicholas C. Rumin

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1996

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution.

Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin

Proceedings of the 1996 European Design and Test Conference, 1996

1994

Inverter models of CMOS gates for supply current and delay evaluation.

Abdolreza Nabavi-Lishi, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Inverter-based Models for Current Analysis of CMOS Logic Circuits.

Abdolreza Nabavi-Lishi, Nicholas C. Rumin

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Delay prediction from resistance-capacitance models of general MOS circuits.

Denis Martin, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Transistor-level estimation of worst-case delays in MOS VLSI circuits.

Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Accuracy of magnitude-class calculations in switch-level modeling.

Eduard Cerny, John P. Hayes, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Delay and bus current evaluation in CMOS logic circuits.

Abdolreza Nabavi-Lishi, Nicholas C. Rumin

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

A recursive technique for computing delays in series-parallel MOS transistor circuits.

Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1989

On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches.

Michel R. Dagenais, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Magnitude classes in switch-level modeling.

Eduard Cerny, John P. Hayes, Nicholas C. Rumin

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Worst-case Delay Estimation of Transistor Groups.

Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Delay computation in switch-level models of non-treelike MOS circuits.

Denis Martin, Nicholas C. Rumin

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986

McBOOLE: A New Procedure for Exact Logic Minimization.

Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits.

Yvon Savaria, Nicholas C. Rumin, Jeremiah F. Hayes, Vinold K. Agarwal

Proc. IEEE, 1986

A Theory for the Design of Soft-Error-Tolerant VLSI Circuits.

Yvon Savaria, Jeremiah F. Hayes, Nicholas C. Rumin, Vinod K. Agarwal

IEEE J. Sel. Areas Commun., 1986

1985

The McBOOLE logic minimizer.

Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

A Design for Machines with Built-In Tolerance to Soft Errors.

Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes

Proceedings of the Proceedings International Test Conference 1984, 1984