Andrea Fedeli

According to our database1, Andrea Fedeli authored at least 15 papers between 2001 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2007
Properties Incompleteness Evaluation by Functional Verification.
IEEE Trans. Computers, 2007

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.
IEEE Des. Test Comput., 2007

SC2SCFL: Automated SystemC to SystemC<sup>FL</sup> Translation.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2005
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

2004
Timed State Space Analysis of Real-Time Preemptive Systems.
IEEE Trans. Software Eng., 2004

A Verification Methodology for Reconfigurable Systems.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

2003
Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools.
Proceedings of the SDL 2003: System Design, 2003

On the Use of a High-Level Fault Model to Check Properties Incompleteness.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Predicting Timeliness of Reactive Systems under Flexible Scheduling.
Proceedings of the 6th International Symposium on Autonomous Decentralized Systems (ISADS 2003), 2003

Modeling Flexible Real Time Systems with Preemptive Time Petri Nets.
Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2003

2002
A 1000X speed up for properties completeness evaluation.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

An error simulation based approach to measure error coverage of formal properties.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Formal Verification Techniques: Industrial Status and Perspectives.
Proceedings of the 2002 Design, 2002

2001
Concrete Impact of Formal Verification on Quality in IP Design and Implementation.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001


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