Graziano Pravadelli

SN Comput. Sci., January, 2024

ICT-Based Solutions for Alzheimer's Disease Care: A Systematic Review.

[BibT_eX]

[DOI]

IEEE Access, 2024

2023

A Low-Cost Wireless Body Area Network for Human Activity Recognition in Healthy Life and Medical Applications.

[BibT_eX]

[DOI]

Ruggero Angelo Bacchin

IEEE Trans. Emerg. Top. Comput., 2023

A Comprehensive Review of Automated Data Annotation Techniques in Human Activity Recognition.

[BibT_eX]

[DOI]

CoRR, 2023

Non-Invasive Monitoring of Alzheimer's patients through WiFi Channel State Information.

[BibT_eX]

[DOI]

Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023

Video Sonification to Support Visually Impaired People: The VISaVIS Approach.

[BibT_eX]

[DOI]

Proceedings of the Image Analysis and Processing - ICIAP 2023, 2023

Fostering Human Activity Recognition Workflows: An Open-Source Baseline Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Digital Health, 2023

Towards Deep Learning-based Occupancy Detection Via WiFi Sensing in Unconstrained Environments.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Exploiting assertions mining and fault analysis to guide RTL-level approximation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Automatic Generation of Assertions for Detection of Firmware Vulnerabilities Through Alignment of Symbolic Sequences.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

HARM: A Hint-Based Assertion Miner.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

WiFiEye - Seeing over WiFi Made Accessible.

[BibT_eX]

[DOI]

CoRR, 2022

Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Assertion-aware approximate computing design exploration on behavioral models.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Risk Assessment and Prediction in Human-Robot Interaction Through Assertion Mining and Pose Estimation.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Integrating Wearable and Camera Based Monitoring in the Digital Twin for Safety Assessment in the Industry 4.0 Era.

[BibT_eX]

[DOI]

Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Practice, 2022

Practical identity recognition using WiFi's Channel State Information.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A freely available system for human activity recognition based on a low-cost body area network.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022

A virtual coaching platform to support therapy compliance in obesity.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022

2021

Estimating indoor occupancy through low-cost BLE devices.

[BibT_eX]

[DOI]

CoRR, 2021

B-HAR: an open-source baseline framework for in depth study of human activity recognition datasets and workflows.

[BibT_eX]

[DOI]

CoRR, 2021

Exploiting Bluetooth Low Energy smart tags for virtual coaching.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level.

[BibT_eX]

[DOI]

Moreno Bragaglio

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

System-level bug explanation through program slicing and instruction clusterization.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

A low-cost BLE-based distance estimation, occupancy detection and counting system.

[BibT_eX]

[DOI]

Fabio Chiarani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A containerized ROS-compliant verification environment for robotic systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Toward a Wearable System for Predicting Freezing of Gait in People Affected by Parkinson's Disease.

[BibT_eX]

[DOI]

Ruggero Angelo Bacchin

Stefano Tamburin

Marco Cristani

IEEE J. Biomed. Health Informatics, 2020

Mangrove: An Inference-Based Dynamic Invariant Mining for GPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Human Activity Recognition Using Inertial, Physiological and Environmental Sensors: A Comprehensive Survey.

[BibT_eX]

[DOI]

IEEE Access, 2020

From Informal Specifications to an ABV Framework for Industrial Firmware Verification.

[BibT_eX]

[DOI]

Moreno Bragaglio

Proceedings of the VLSI-SoC: Design Trends, 2020

MIST: monitor generation from informal specifications for firmware verification.

[BibT_eX]

[DOI]

Moreno Bragaglio

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Joint Distribution and Transitions of Pain and Activity in Critically Ill Patients.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019

Engineering of an Effective Automatic Dynamic Assertion Mining Platform.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A model-based design flow for Dynamic Partial Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Enrico Giordano

Federico Di Marco

Proceedings of the 2019 IEEE International Conference on Systems, Man and Cybernetics, 2019

RTL Assertion Mining with Automated RTL-to-TLM Abstraction.

[BibT_eX]

[DOI]

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

An indoor localization system to detect areas causing the freezing of gait in Parkinsonians.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

A graph-based approach for mobile localization exploiting real and virtual landmarks.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Symbolic assertion mining for security validation.

[BibT_eX]

[DOI]

Valeria Bertacco

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Hardware/Software Codesign., 2017

Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models.

[BibT_eX]

[DOI]

Alessandro Menon

ACM Trans. Embed. Comput. Syst., 2017

Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL.

[BibT_eX]

[DOI]

Riccardo Zucchelli

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

A-TEAM: Automatic template-based assertion miner.

[BibT_eX]

[DOI]

Nicolò Dalla Riva

Proceedings of the 54th Annual Design Automation Conference, 2017

DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress).

[BibT_eX]

[DOI]

Valeria Bertacco

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016

Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software.

[BibT_eX]

[DOI]

Davide Ferraretto

J. Electron. Test., 2016

Stimuli generation through invariant mining for black-box verification.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Fault model qualification by assertion mining.

[BibT_eX]

[DOI]

Jacopo Mocci

Proceedings of the 17th Latin-American Test Symposium, 2016

Dynamic service synthesis and switching for medical IoT and ambient assisted living.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Automatic generation of self-adaptive transactors from PSL assertions.

[BibT_eX]

[DOI]

Francesco Stefanni

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Automatic generation of power state machines through dynamic mining of temporal assertions.

[BibT_eX]

[DOI]

Mirella Negro Marcigaglia

Ivan Zandona

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.

[BibT_eX]

[DOI]

J. Electron. Test., 2015

On the estimation of assertion interestingness.

[BibT_eX]

[DOI]

Tara Ghasempouri

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A time-window based approach for dynamic assertions mining on control signals.

[BibT_eX]

[DOI]

Francesca Filini

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Efficient fault injection in QEMU.

[BibT_eX]

[DOI]

Davide Ferraretto

Proceedings of the 16th Latin-American Test Symposium, 2015

Exploiting GPU architectures for dynamic invariant mining.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Automatic extraction of assertions from execution traces of behavioural models.

[BibT_eX]

[DOI]

Tara Ghasempouri

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RTL property abstraction for TLM assertion-based verification.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A parallelizable approach for mining likely invariants.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014

Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms.

[BibT_eX]

[DOI]

Alessandro Lonardi

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms.

[BibT_eX]

[DOI]

Filippo Cucchetto

Alessandro Lonardi

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Simplified stimuli generation for scenario and assertion based verification.

[BibT_eX]

[DOI]

Mirella Negro Marcigaglia

Proceedings of the 15th Latin American Test Workshop, 2014

On the reuse of RTL assertions in SystemC TLM verification.

[BibT_eX]

[DOI]

Proceedings of the 15th Latin American Test Workshop, 2014

2013

UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

On the integration of model-driven design and dynamic assertion-based verification for embedded software.

[BibT_eX]

[DOI]

J. Syst. Softw., 2013

Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software.

[BibT_eX]

[DOI]

Davide Ferraretto

Proceedings of the 18th IEEE European Test Symposium, 2013

Automatic generation of compact formal properties for effective error detection.

[BibT_eX]

[DOI]

Michele Bertasi

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012

Time-Constraint-Aware Optimization of Assertions in Embedded Software.

[BibT_eX]

[DOI]

Viacheslav Izosimov

J. Electron. Test., 2012

On the Reuse of TLM Mutation Analysis at RTL.

[BibT_eX]

[DOI]

Valerio Guarnieri

J. Electron. Test., 2012

A formal support for homogeneous simulation of heterogeneous embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Accurate profiling of oracles for self-checking time-constrained embedded software.

[BibT_eX]

[DOI]

Simone Bronuzzi

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Combining dynamic slicing and mutation operators for ESL correction.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

On the use of assertions for embedded-software dynamic verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Enabling dynamic assertion-based verification of embedded software through model-driven design.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A testbench specification language for SystemC verification.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Dynamic property mining for embedded software.

[BibT_eX]

[DOI]

Marco Bonato

Masahiro Fujita

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Reusing of Properties after Discretization of Hybrid Automata.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

EFSM-based model-driven approach to concolic testing of system-level design.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Mutation analysis for SystemC designs at TLM.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Model-driven design and validation of embedded software.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Interactive presentation abstract: Assertion-based verification in embedded-software design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Interactive presentation abstract: Reusing of properties after discretization of hybrid automata.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the 16th European Test Symposium, 2011

2010

HIFSuite: Tools for HDL Code Conversion and Manipulation.

[BibT_eX]

[DOI]

Alessandro Venturelli

EURASIP J. Embed. Syst., 2010

DDPSL: An easy way of defining properties.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Semi-formal functional verification by EFSM traversing via NuSMV.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

HIFSuite: Tools for HDL code conversion and manipulation.

[BibT_eX]

[DOI]

Alessandro Venturelli

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Vacuity analysis for property qualification by mutation of checkers.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

RTOS-aware refinement for TLM2.0-based HW/SW designs.

[BibT_eX]

[DOI]

Markus Becker

Proceedings of the Design, Automation and Test in Europe, 2010

Abstraction of RTL IPs into embedded software.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

A cosimulation methodology for HW/SW validation and performance estimation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

On the Mutation Analysis of SystemC TLM-2.0 Standard.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

The role of mutation analysis for property qualification.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

On the Functional Qualification of a Platform Model.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

The impact of EFSM composition on functional ATPG.

[BibT_eX]

[DOI]

Davide Bresolin

Tiziano Villa

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Correct-by-construction generation of device drivers based on RTL testbenches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Functional qualification of TLM verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Vacuity Analysis by Fault Simulation.

[BibT_eX]

[DOI]

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

The role of parallel simulation in functional verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An optimized CLP-based technique for generating propagation sequences.

[BibT_eX]

[DOI]

Proceedings of the 2008 East-West Design & Test Symposium, 2008

RTL-TLM equivalence checking based on simulation.

[BibT_eX]

[DOI]

Proceedings of the 2008 East-West Design & Test Symposium, 2008

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Properties Incompleteness Evaluation by Functional Verification.

[BibT_eX]

[DOI]

Andrea Fedeli

IEEE Trans. Computers, 2007

Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Too Few or Too Many Properties? Measure it by ATPG!

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

A CLP-Based Functional ATPG for Extended FSMs.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Towards Equivalence Checking Between TLM and RTL Models.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

A smooth refinement flow for co-designing HW and SW threads.

[BibT_eX]

[DOI]

Paolo Destro

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Incremental ABV for functional validation of TL-to-RTL design refinement.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Improving Gate-Level ATPG by Traversing Concurrent EFSMs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Hardware Design and Simulation for Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Hardware Verification, 2006

A methodology for abstracting RTL designs into TL descriptions.

[BibT_eX]

[DOI]

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

EFSM Manipulation to Increase High-Level ATPG Effectiveness.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FATE: a Functional ATPG to Traverse Unstabilized EFSMs.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Logic-level mapping of high-level faults.

[BibT_eX]

[DOI]

Integr., 2005

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2005

A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

On the use of a high-level fault model to analyze logical consequence of properties.

[BibT_eX]

[DOI]

Stefano Brait

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Functional Verification of Networked Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An EFSM-based approach for functional ATPG.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Coverage of formal properties based on a high-level fault model and functional ATPG.

[BibT_eX]

[DOI]

Franco Toto

Proceedings of the 10th European Test Symposium, 2005

2004

A Verification Methodology for Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Functional verification based on the EFSM model.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Logic-level analysis of high-level faults.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

At-Speed Functional Verification of Programmable Devices.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A timing-accurate HW/SW co-simulation of an ISS with SystemC.

[BibT_eX]

[DOI]

Luca Formaggio

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Using functional verification to evaluate the accuracy of model checking applied to embedded systems.

[BibT_eX]

[DOI]

PhD thesis, 2003

Identification of design errors through functional testing.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

A SystemC-based Framework for Properties Incompleteness Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

On the Use of a High-Level Fault Model to Check Properties Incompleteness.

[BibT_eX]

[DOI]

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Redundant functional faults reduction by saboteurs synthesis [logic verification].

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Mixing ATPG and property checking for testing HW/SW interfaces.

[BibT_eX]

[DOI]

Alessandro Fin

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002

A 1000X speed up for properties completeness evaluation.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

An error simulation based approach to measure error coverage of formal properties.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

AMLETO: a multi-language environment for functional test generation.

[BibT_eX]

[DOI]

Alessandro Fin