Graziano Pravadelli

According to our database1, Graziano Pravadelli authored at least 110 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
An indoor localization system to detect areas causing the freezing of gait in Parkinsonians.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A graph-based approach for mobile localization exploiting real and virtual landmarks.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Symbolic assertion mining for security validation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models.
ACM Trans. Embedded Comput. Syst., 2017

Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

A-TEAM: Automatic template-based assertion miner.
Proceedings of the 54th Annual Design Automation Conference, 2017

DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress).
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software.
J. Electronic Testing, 2016

Stimuli generation through invariant mining for black-box verification.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Fault model qualification by assertion mining.
Proceedings of the 17th Latin-American Test Symposium, 2016

Dynamic service synthesis and switching for medical IoT and ambient assisted living.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Automatic generation of self-adaptive transactors from PSL assertions.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Automatic generation of power state machines through dynamic mining of temporal assertions.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.
J. Electronic Testing, 2015

On the estimation of assertion interestingness.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A time-window based approach for dynamic assertions mining on control signals.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Efficient fault injection in QEMU.
Proceedings of the 16th Latin-American Test Symposium, 2015

Exploiting GPU architectures for dynamic invariant mining.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Automatic extraction of assertions from execution traces of behavioural models.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RTL property abstraction for TLM assertion-based verification.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A parallelizable approach for mining likely invariants.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.
IEEE Trans. Computers, 2014

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Simplified stimuli generation for scenario and assertion based verification.
Proceedings of the 15th Latin American Test Workshop, 2014

On the reuse of RTL assertions in SystemC TLM verification.
Proceedings of the 15th Latin American Test Workshop, 2014

2013
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration.
IEEE Trans. Computers, 2013

On the integration of model-driven design and dynamic assertion-based verification for embedded software.
Journal of Systems and Software, 2013

Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software.
Proceedings of the 18th IEEE European Test Symposium, 2013

Automatic generation of compact formal properties for effective error detection.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Time-Constraint-Aware Optimization of Assertions in Embedded Software.
J. Electronic Testing, 2012

On the Reuse of TLM Mutation Analysis at RTL.
J. Electronic Testing, 2012

A formal support for homogeneous simulation of heterogeneous embedded systems.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Accurate profiling of oracles for self-checking time-constrained embedded software.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Combining dynamic slicing and mutation operators for ESL correction.
Proceedings of the 17th IEEE European Test Symposium, 2012

On the use of assertions for embedded-software dynamic verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Enabling dynamic assertion-based verification of embedded software through model-driven design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A testbench specification language for SystemC verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Dynamic property mining for embedded software.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions.
IEEE Trans. Computers, 2011

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.
J. Electronic Testing, 2011

Reusing of Properties after Discretization of Hybrid Automata.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

EFSM-based model-driven approach to concolic testing of system-level design.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Model-driven design and validation of embedded software.
Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Interactive presentation abstract: Assertion-based verification in embedded-software design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Interactive presentation abstract: Reusing of properties after discretization of hybrid automata.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.
Proceedings of the 16th European Test Symposium, 2011

2010
HIFSuite: Tools for HDL Code Conversion and Manipulation.
EURASIP J. Emb. Sys., 2010

DDPSL: An easy way of defining properties.
Proceedings of the 28th International Conference on Computer Design, 2010

Semi-formal functional verification by EFSM traversing via NuSMV.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

HIFSuite: Tools for HDL code conversion and manipulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Vacuity analysis for property qualification by mutation of checkers.
Proceedings of the Design, Automation and Test in Europe, 2010

RTOS-aware refinement for TLM2.0-based HW/SW designs.
Proceedings of the Design, Automation and Test in Europe, 2010

Abstraction of RTL IPs into embedded software.
Proceedings of the 47th Design Automation Conference, 2010

2009
A cosimulation methodology for HW/SW validation and performance estimation.
ACM Trans. Design Autom. Electr. Syst., 2009

On the Mutation Analysis of SystemC TLM-2.0 Standard.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

The role of mutation analysis for property qualification.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

On the Functional Qualification of a Platform Model.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

The impact of EFSM composition on functional ATPG.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Correct-by-construction generation of device drivers based on RTL testbenches.
Proceedings of the Design, Automation and Test in Europe, 2009

Functional qualification of TLM verification.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.
ACM Trans. Design Autom. Electr. Syst., 2008

Vacuity Analysis by Fault Simulation.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

The role of parallel simulation in functional verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An optimized CLP-based technique for generating propagation sequences.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

RTL-TLM equivalence checking based on simulation.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Properties Incompleteness Evaluation by Functional Verification.
IEEE Trans. Computers, 2007

Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
IET Computers & Digital Techniques, 2007

Too Few or Too Many Properties? Measure it by ATPG!
J. Electronic Testing, 2007

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.
IEEE Design & Test of Computers, 2007

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
CoRR, 2007

A CLP-Based Functional ATPG for Extended FSMs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Towards Equivalence Checking Between TLM and RTL Models.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

A smooth refinement flow for co-designing HW and SW threads.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Incremental ABV for functional validation of TL-to-RTL design refinement.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Improving Gate-Level ATPG by Traversing Concurrent EFSMs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Hardware Design and Simulation for Verification.
Proceedings of the Formal Methods for Hardware Verification, 2006

A methodology for abstracting RTL designs into TL descriptions.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

EFSM Manipulation to Increase High-Level ATPG Effectiveness.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
Proceedings of the 11th European Test Symposium, 2006

On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Logic-level mapping of high-level faults.
Integration, 2005

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey.
International Journal of Parallel Programming, 2005

A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

On the use of a high-level fault model to analyze logical consequence of properties.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Functional Verification of Networked Embedded Systems.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An EFSM-based approach for functional ATPG.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Coverage of formal properties based on a high-level fault model and functional ATPG.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

2004
A Verification Methodology for Reconfigurable Systems.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Functional verification based on the EFSM model.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Logic-level analysis of high-level faults.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?
Proceedings of the 9th European Test Symposium, 2004

At-Speed Functional Verification of Programmable Devices.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems.
Proceedings of the 2004 Design, 2004

A timing-accurate HW/SW co-simulation of an ISS with SystemC.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Identification of design errors through functional testing.
IEEE Trans. Reliability, 2003

A SystemC-based Framework for Properties Incompleteness Evaluation.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

On the Use of a High-Level Fault Model to Check Properties Incompleteness.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Redundant functional faults reduction by saboteurs synthesis [logic verification].
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Mixing ATPG and property checking for testing HW/SW interfaces.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
A 1000X speed up for properties completeness evaluation.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

An error simulation based approach to measure error coverage of formal properties.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
AMLETO: a multi-language environment for functional test generation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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