Franco Fummi

According to our database1, Franco Fummi authored at least 262 papers between 1993 and 2018.

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Bibliography

2018
Pro++: A Profiling Framework for Primitive-Based GPU Programming.
IEEE Trans. Emerging Topics Comput., 2018

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Network Synthesis for Distributed Embedded Systems.
IEEE Trans. Computers, 2018

Cyber-Physical Systems Integration in a Production Line Simulator.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Framework for the Design and Simulation of Embedded Vision Applications Based on OpenVX and ROS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Simulation-based Holistic Functional Safety Assessment for Networked Cyber-Physical Systems.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Transaction-level Functional Mockup Units for Cyber-Physical Virtual Platforms.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Efficient Simulation of Faults in Networked Cyber-Physical Systems.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Automatic integration of cycle-accurate descriptions with continuous-time models for cyber-physical virtual platforms.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework.
Handbook of Hardware/Software Codesign, 2017

A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Fault analysis in analog circuits through language manipulation and abstraction.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Automatic generation of cycle-accurate Simulink blocks from hdl ips.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

A homogeneous framework for AMS languages instrumentation, abstraction and simulation.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Automatic abstraction of multi-discipline analog models for efficient functional simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Analog fault testing through abstraction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Power-aware Performance Tuning of GPU Applications Through Microbenchmarking.
Proceedings of the 54th Annual Design Automation Conference, 2017

Virtual prototyping of smart systems through automatic abstraction and mixed-signal scheduling.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Erratum to "Model-Driven Design of Network Aspects of Distributed Embedded Systems".
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Code Manipulation for Virtual Platform Integration.
IEEE Trans. Computers, 2016

MIPP: A microbenchmark suite for performance, power, and energy consumption characterization of GPU architectures.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

A SystemC-based platform for assertion-based verification and mutation analysis in systems biology.
Proceedings of the 17th Latin-American Test Symposium, 2016

A unifying flow to ease smart systems integration.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

SyQUAL: a platform for qualitative modelling and simulation of biological systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Integration of mixed-signal components into virtual platforms for holistic simulation of smart systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fine-grained performance model for GPU architectures.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications.
ACM Trans. Design Autom. Electr. Syst., 2015

Model-Driven Design of Network Aspects of Distributed Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.
Sensors, 2015

Simulation alternatives for the verification of networked cyber-physical systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.
J. Electronic Testing, 2015

HDL code generation from UML/MARTE sequence diagrams for verification and synthesis.
Design Autom. for Emb. Sys., 2015

An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Extensions to the UML profile for MARTE for distributed embedded systems.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

2014
Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.
IEEE Trans. Computers, 2014

A framework for design space exploration and performance analysis of networked embedded systems.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

Hardware Synthesis from Software-Oriented UML Descriptions.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

On the reuse of RTL assertions in SystemC TLM verification.
Proceedings of the 15th Latin American Test Workshop, 2014

An open-source framework for formal specification and simulation of electrical energy systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Multi-domain simulation as a foundation for the engineering of smart systems: Challenges and the SMAC vision.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Simulation Alternatives for Modeling Networked Cyber-Physical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A cross-level verification methodology for digital IPs augmented with embedded timing monitors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Moving from co-simulation to simulation for effective smart systems design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Panel: Future SoC verification methodology: UVM evolution or revolution?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Dynamic Modeling and Simulation of Leukocyte Integrin Activation through an Electronic Design Automation Framework.
Proceedings of the Computational Methods in Systems Biology, 2014

2013
Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration.
IEEE Trans. Computers, 2013

On the integration of model-driven design and dynamic assertion-based verification for embedded software.
Journal of Systems and Software, 2013

On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation.
J. Electronic Testing, 2013

A Toolchain for UML-based Modeling and Simulation of Networked Embedded Systems.
Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013

Automatic Network Protocol Synthesis from UML Sequence Diagrams.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Code generation alternatives to reduce heterogeneous embedded systems to homogeneity.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Model-driven design for the development of multi-platform smartphone applications.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

RTL IP abstraction into optimized embedded software.
Proceedings of the East-West Design & Test Symposium, 2013

Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software.
Proceedings of the 18th IEEE European Test Symposium, 2013

UML-Based Modeling and Simulation of Environmental Effects in Networked Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.
Proceedings of the Design, Automation and Test in Europe, 2013

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

On the automatic generation of GPU-oriented software applications from RTL IPs.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Time-Constraint-Aware Optimization of Assertions in Embedded Software.
J. Electronic Testing, 2012

On the Reuse of TLM Mutation Analysis at RTL.
J. Electronic Testing, 2012

FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction.
J. Electronic Testing, 2012

HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels.
Design Autom. for Emb. Sys., 2012

A formal support for homogeneous simulation of heterogeneous embedded systems.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

On the Reuse of RTL IPs for SysML Model Generation.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Accurate profiling of oracles for self-checking time-constrained embedded software.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Energy aware TLM platform simulation via RTL abstraction.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

On the automatic synthesis of parallel SW from RTL models of hardware IPs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Combining dynamic slicing and mutation operators for ESL correction.
Proceedings of the 17th IEEE European Test Symposium, 2012

Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

On the use of assertions for embedded-software dynamic verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Enabling dynamic assertion-based verification of embedded software through model-driven design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Refinement of UML/MARTE models for the design of networked embedded systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SAGA: SystemC acceleration on GPU architectures.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Dynamic property mining for embedded software.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions.
IEEE Trans. Computers, 2011

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.
J. Electronic Testing, 2011

Communication-aware middleware-based design-space exploration for Networked Embedded Systems.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Reusing of Properties after Discretization of Hybrid Automata.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

EFSM-based model-driven approach to concolic testing of system-level design.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Communication-aware design flow for dependable networked embedded systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Model-driven design and validation of embedded software.
Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Interactive presentation abstract: Assertion-based verification in embedded-software design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Interactive presentation abstract: Reusing of properties after discretization of hybrid automata.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Efficient implementation and abstraction of systemc data types for fast simulation.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.
Proceedings of the 16th European Test Symposium, 2011

Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.
Proceedings of the 16th European Test Symposium, 2011

Automatic Interface Generation for Component Reuse in HW-SW Partitioning.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
System/network design-space exploration based on TLM for networked embedded systems.
ACM Trans. Embedded Comput. Syst., 2010

HIFSuite: Tools for HDL Code Conversion and Manipulation.
EURASIP J. Emb. Sys., 2010

Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Network-adaptive management of computation energy in wireless sensor networks.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

DDPSL: An easy way of defining properties.
Proceedings of the 28th International Conference on Computer Design, 2010

Semi-formal functional verification by EFSM traversing via NuSMV.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

HIFSuite: Tools for HDL code conversion and manipulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Modeling of Communication Infrastructure for Design-Space Exploration.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Exploration of Network Alternatives for Middleware-centric Embedded System Design.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Vacuity analysis for property qualification by mutation of checkers.
Proceedings of the Design, Automation and Test in Europe, 2010

RTOS-aware refinement for TLM2.0-based HW/SW designs.
Proceedings of the Design, Automation and Test in Europe, 2010

Abstraction of RTL IPs into embedded software.
Proceedings of the 47th Design Automation Conference, 2010

2009
A cosimulation methodology for HW/SW validation and performance estimation.
ACM Trans. Design Autom. Electr. Syst., 2009

Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

On the Mutation Analysis of SystemC TLM-2.0 Standard.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

A SystemC-centric approach for simulation and generation of WSN applications targeted to ZigBee.
Proceedings of the 6th Annual International Conference on Mobile and Ubiquitous Systems: Computing, 2009

The role of mutation analysis for property qualification.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

On the Functional Qualification of a Platform Model.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

The impact of EFSM composition on functional ATPG.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Networked embedded system applications design driven by an abstract middleware environment.
Proceedings of the Design, Automation and Test in Europe, 2009

Flexible energy-aware simulation of heterogenous wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2009

Correct-by-construction generation of device drivers based on RTL testbenches.
Proceedings of the Design, Automation and Test in Europe, 2009

Functional qualification of TLM verification.
Proceedings of the Design, Automation and Test in Europe, 2009

Automatic customization of device drivers for IP-cores used with assorted CPU organizations.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.
ACM Trans. Design Autom. Electr. Syst., 2008

Vacuity Analysis by Fault Simulation.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

The role of parallel simulation in functional verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

A HW/SW co-simulation framework for the verification of multi-CPU systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An energy-aware co-simulation framework for the design of wireless sensor networks.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

SystemC Simulation of Networked Embedded Systems.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems.
Proceedings of the Forum on specification and Design Languages, 2008

An optimized CLP-based technique for generating propagation sequences.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

RTL-TLM equivalence checking based on simulation.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

Network Fault Model for Dependability Assessment of Networked Embedded Systems.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.
Proceedings of the Design, Automation and Test in Europe, 2008

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Properties Incompleteness Evaluation by Functional Verification.
IEEE Trans. Computers, 2007

eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions.
JCM, 2007

Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
IET Computers & Digital Techniques, 2007

Too Few or Too Many Properties? Measure it by ATPG!
J. Electronic Testing, 2007

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.
IEEE Design & Test of Computers, 2007

SystemC co-simulation for core-based embedded systems.
Design Autom. for Emb. Sys., 2007

A CLP-Based Functional ATPG for Extended FSMs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Towards Equivalence Checking Between TLM and RTL Models.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Co-simulation framework for the Angel platform.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

AME: an abstract middleware environment for validating networked embedded systems applications.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Interactive presentation: A middleware-centric design flow for networked embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A smooth refinement flow for co-designing HW and SW threads.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Incremental ABV for functional validation of TL-to-RTL design refinement.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Yield-aware placement optimization.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Modeling and simulation alternatives for the design of networked embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Guest Editor's Introduction.
International Journal of Parallel Programming, 2006

Improving Gate-Level ATPG by Traversing Concurrent EFSMs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Hardware Design and Simulation for Verification.
Proceedings of the Formal Methods for Hardware Verification, 2006

A methodology for abstracting RTL designs into TL descriptions.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

EFSM Manipulation to Increase High-Level ATPG Effectiveness.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

On the Automatic Transactor Generation for TLM-based Design Flows.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

ISS-centric modular HW/SW co-simulation.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
Proceedings of the 11th European Test Symposium, 2006

Modeling and simulation of mobile gateways interacting with wireless sensor networks.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

TLM/network design space exploration for networked embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Logic-level mapping of high-level faults.
Integration, 2005

Editorial.
International Journal of Parallel Programming, 2005

A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Embedded SW Design Issues for Distributed Applications on Mobile Terminals.
Proceedings of the 2nd Annual International Conference on Mobile and Ubiquitous Systems (MobiQuitous 2005), 2005

On the use of a high-level fault model to analyze logical consequence of properties.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Functional Verification of Networked Embedded Systems.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An EFSM-based approach for functional ATPG.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Coverage of formal properties based on a high-level fault model and functional ATPG.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation.
Proceedings of the 2005 Design, 2005

2004
A Verification Methodology for Reconfigurable Systems.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Functional verification based on the EFSM model.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Logic-level analysis of high-level faults.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?
Proceedings of the 9th European Test Symposium, 2004

At-Speed Functional Verification of Programmable Devices.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Heterogeneous Co-Simulation of Networked Embedded Systems.
Proceedings of the 2004 Design, 2004

Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC.
Proceedings of the 2004 Design, 2004

Modeling and Analysis of Heterogeneous Industrial Networks Architectures.
Proceedings of the 2004 Design, 2004

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems.
Proceedings of the 2004 Design, 2004

A timing-accurate HW/SW co-simulation of an ISS with SystemC.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Identification of design errors through functional testing.
IEEE Trans. Reliability, 2003

A Remote Methodology for Embedded Systems Design and Validation.
Design Autom. for Emb. Sys., 2003

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.
IEEE Computer, 2003

A SystemC-based Framework for Properties Incompleteness Evaluation.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

On the Use of a High-Level Fault Model to Check Properties Incompleteness.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

The Confluence of Manufacturing Test and Design Validation.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Redundant functional faults reduction by saboteurs synthesis [logic verification].
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Mixing ATPG and property checking for testing HW/SW interfaces.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

LAERTE++: an Object Oriented High-level TPG for SystemC Designs.
Proceedings of the Forum on specification and Design Languages, 2003

Estimation of Bus Performance for a Tuplespace in an Embedded Architecture.
Proceedings of the 2003 Design, 2003

A timing-accurate modeling and simulation environment for networked embedded systems.
Proceedings of the 40th Design Automation Conference, 2003

2002
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.
IEEE Trans. Computers, 2002

Behavioral test generation for the selection of BIST logic.
Journal of Systems Architecture, 2002

A combined approach to validate the design of embedded network devices.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A fault tolerant incremental design methodology.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Genetic Testing Framework for Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2002), 2002

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A 1000X speed up for properties completeness evaluation.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Protected IP-core test generation.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

An error simulation based approach to measure error coverage of formal properties.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002

Emulation-Based Design Errors Identification.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach.
J. Electronic Testing, 2001

AMLETO: a multi-language environment for functional test generation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Soft-cores generation by instruction set analysis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Functional test generation for behaviorally sequential models.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

SystemC: a homogenous environment to test embedded systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Symbolic optimization of interacting controllers based onredundancy identification and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A Hierarchical Test Generation Approach for Large Controllers.
IEEE Trans. Computers, 2000

An extended-UIO-based method for protocol conformance testing.
Journal of Systems Architecture, 2000

Testability Alternatives Exploration through Functional Testing.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An Application of Genetic Algorithms and BDDs to Functional Testing.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

BIST Architectures Selection Based on Behavioral Testing.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

A VHDL Error Simulator for Functional Test Generation.
Proceedings of the 2000 Design, 2000

A Web-CAD methodology for IP-core analysis and simulation.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.
IEEE Trans. Computers, 1999

Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Power Characterization of LFSRs.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Symbolic Functional Vector Generation for VHDL Specifications.
Proceedings of the 1999 Design, 1999

1998
Automatic generation of error control codes for computer applications.
IEEE Trans. VLSI Syst., 1998

Testability analysis and behavioral testing of the Hopfield neural paradigm.
IEEE Trans. VLSI Syst., 1998

Implicit test generation for behavioral VHDL models.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Automatic VHDL restructuring for RTL synthesis optimization and testability improvement.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Power Estimation of Behavioral Descriptions.
Proceedings of the 1998 Design, 1998

1997
Functional design for testability of control-dominated architectures.
ACM Trans. Design Autom. Electr. Syst., 1997

A complete testing strategy based on interacting and hierarchical FSMs.
Integration, 1997

Testing Core-Based Systems: A Symbolic Methodology.
IEEE Design & Test of Computers, 1997

Implicit test pattern generation constrained to cellular automata embedding.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

How an "Evolving" Fault Model Improves the Behavioral Test Generation.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
FsmTest: Functional test generation for sequential circuits.
Integration, 1996

Implicit Test Sequences Compaction for Decreasing Test Application Cos.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

BDD-based testability estimation of VHDL designs.
Proceedings of the conference on European design automation, 1996

A Parametric Design of a Built-in Self-Test FIFO Embedded Memory.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
Proceedings of the 33st Conference on Design Automation, 1996

1995
TIES: A testability increase expert system for VLSI design.
J. Electronic Testing, 1995

A BDD Based Algorithm for Detecting Difficult Faults.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Synthesis for testability of large complexity controllers.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Testable synthesis of high complex control devices.
Proceedings of the Proceedings EURO-DAC'95, 1995

Sequential logic minimization based on functional testability.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Two-Dimensional Sequential Array Architectures: Design for Testability Approaches.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Functional Approach to Delay Faults Test Generation for Sequential Circuits.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

From Behavioral Description to Systolic Array Based Architectures.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
FSM fault models impact on test performances.
Microprocessing and Microprogramming, 1993

A design methodology for the correct specification of VLSI systems.
Microprocessing and Microprogramming, 1993

Functional Testing and Constrained Synthesis of Sequential Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Functional Fault Models and Gate Level Coverage for Sequential Architectures.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Fault Detection in Sequential Circuits through Functional Testing.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993


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